b10700d826
These registers have a different format for pa2.0. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
112 lines
3.2 KiB
C
112 lines
3.2 KiB
C
/*
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* Helpers for HPPA system instructions.
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/timer.h"
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#include "sysemu/runstate.h"
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void HELPER(write_interval_timer)(CPUHPPAState *env, target_ulong val)
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{
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HPPACPU *cpu = env_archcpu(env);
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uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint64_t timeout;
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/*
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* Even in 64-bit mode, the comparator is always 32-bit. But the
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* value we expose to the guest is 1/4 of the speed of the clock,
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* so moosh in 34 bits.
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*/
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timeout = deposit64(current, 0, 34, (uint64_t)val << 2);
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/* If the mooshing puts the clock in the past, advance to next round. */
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if (timeout < current + 1000) {
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timeout += 1ULL << 34;
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}
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cpu->env.cr[CR_IT] = timeout;
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timer_mod(cpu->alarm_timer, timeout);
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}
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void HELPER(halt)(CPUHPPAState *env)
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{
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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helper_excp(env, EXCP_HLT);
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}
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void HELPER(reset)(CPUHPPAState *env)
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{
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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helper_excp(env, EXCP_HLT);
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}
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target_ulong HELPER(swap_system_mask)(CPUHPPAState *env, target_ulong nsm)
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{
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target_ulong psw = env->psw;
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/*
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* Setting the PSW Q bit to 1, if it was not already 1, is an
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* undefined operation.
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*
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* However, HP-UX 10.20 does this with the SSM instruction.
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* Tested this on HP9000/712 and HP9000/785/C3750 and both
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* machines set the Q bit from 0 to 1 without an exception,
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* so let this go without comment.
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*/
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env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM);
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return psw & PSW_SM;
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}
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void HELPER(rfi)(CPUHPPAState *env)
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{
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env->iasq_f = (uint64_t)env->cr[CR_IIASQ] << 32;
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env->iasq_b = (uint64_t)env->cr_back[0] << 32;
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env->iaoq_f = env->cr[CR_IIAOQ];
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env->iaoq_b = env->cr_back[1];
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/*
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* For pa2.0, IIASQ is the top bits of the virtual address.
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* To recreate the space identifier, remove the offset bits.
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*/
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if (hppa_is_pa20(env)) {
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env->iasq_f &= ~env->iaoq_f;
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env->iasq_b &= ~env->iaoq_b;
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}
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cpu_hppa_put_psw(env, env->cr[CR_IPSW]);
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}
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void HELPER(getshadowregs)(CPUHPPAState *env)
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{
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env->gr[1] = env->shadow[0];
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env->gr[8] = env->shadow[1];
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env->gr[9] = env->shadow[2];
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env->gr[16] = env->shadow[3];
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env->gr[17] = env->shadow[4];
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env->gr[24] = env->shadow[5];
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env->gr[25] = env->shadow[6];
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}
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void HELPER(rfi_r)(CPUHPPAState *env)
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{
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helper_getshadowregs(env);
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helper_rfi(env);
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}
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