329 lines
9.2 KiB
C
329 lines
9.2 KiB
C
/*
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* QEMU Ultrasparc APB PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* XXX This file and most of its contents are somewhat misnamed. The
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Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
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the secondary PCI bridge. */
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#include "sysbus.h"
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#include "pci.h"
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/* debug APB */
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//#define DEBUG_APB
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#ifdef DEBUG_APB
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#define APB_DPRINTF(fmt, ...) \
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do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define APB_DPRINTF(fmt, ...)
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#endif
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/*
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* Chipset docs:
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* PBM: "UltraSPARC IIi User's Manual",
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* http://www.sun.com/processors/manuals/805-0087.pdf
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*
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* APB: "Advanced PCI Bridge (APB) User's Manual",
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* http://www.sun.com/processors/manuals/805-1251.pdf
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*/
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h"
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typedef struct APBState {
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SysBusDevice busdev;
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PCIHostState host_state;
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} APBState;
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static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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APBState *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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APB_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
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val);
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s->host_state.config_reg = val;
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}
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static uint32_t pci_apb_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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APBState *s = opaque;
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uint32_t val;
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val = s->host_state.config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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APB_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
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val);
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return val;
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}
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static CPUWriteMemoryFunc * const pci_apb_config_write[] = {
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&pci_apb_config_writel,
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&pci_apb_config_writel,
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&pci_apb_config_writel,
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};
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static CPUReadMemoryFunc * const pci_apb_config_read[] = {
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&pci_apb_config_readl,
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&pci_apb_config_readl,
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&pci_apb_config_readl,
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};
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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//PCIBus *s = opaque;
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switch (addr & 0x3f) {
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case 0x00: // Control/Status
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case 0x10: // AFSR
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case 0x18: // AFAR
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case 0x20: // Diagnostic
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case 0x28: // Target address space
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// XXX
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default:
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break;
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}
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}
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static uint32_t apb_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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//PCIBus *s = opaque;
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uint32_t val;
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switch (addr & 0x3f) {
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case 0x00: // Control/Status
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case 0x10: // AFSR
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case 0x18: // AFAR
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case 0x20: // Diagnostic
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case 0x28: // Target address space
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// XXX
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default:
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val = 0;
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break;
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}
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return val;
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}
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static CPUWriteMemoryFunc * const apb_config_write[] = {
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&apb_config_writel,
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&apb_config_writel,
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&apb_config_writel,
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};
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static CPUReadMemoryFunc * const apb_config_read[] = {
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&apb_config_readl,
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&apb_config_readl,
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&apb_config_readl,
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};
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static CPUWriteMemoryFunc * const pci_apb_write[] = {
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&pci_host_data_writeb,
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&pci_host_data_writew,
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&pci_host_data_writel,
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};
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static CPUReadMemoryFunc * const pci_apb_read[] = {
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&pci_host_data_readb,
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&pci_host_data_readw,
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&pci_host_data_readl,
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};
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outb(addr & IOPORTS_MASK, val);
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}
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static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outw(addr & IOPORTS_MASK, val);
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}
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static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outl(addr & IOPORTS_MASK, val);
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}
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static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inb(addr & IOPORTS_MASK);
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return val;
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}
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static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inw(addr & IOPORTS_MASK);
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return val;
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}
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static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inl(addr & IOPORTS_MASK);
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return val;
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}
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static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
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&pci_apb_iowriteb,
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&pci_apb_iowritew,
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&pci_apb_iowritel,
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};
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static CPUReadMemoryFunc * const pci_apb_ioread[] = {
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&pci_apb_ioreadb,
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&pci_apb_ioreadw,
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&pci_apb_ioreadl,
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};
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/* The APB host has an IRQ line for each IRQ line of each slot. */
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static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
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}
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static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int bus_offset;
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if (pci_dev->devfn & 1)
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bus_offset = 16;
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else
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bus_offset = 0;
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return bus_offset + irq_num;
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}
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static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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/* PCI IRQ map onto the first 32 INO. */
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qemu_set_irq(pic[irq_num], level);
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}
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PCIBus *pci_apb_init(target_phys_addr_t special_base,
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target_phys_addr_t mem_base,
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qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
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{
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DeviceState *dev;
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SysBusDevice *s;
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APBState *d;
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/* Ultrasparc PBM main bus */
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dev = qdev_create(NULL, "pbm");
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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/* apb_config */
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sysbus_mmio_map(s, 0, special_base + 0x2000ULL);
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/* pci_ioport */
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sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
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/* mem_config: XXX size should be 4G-prom */
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sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
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/* mem_data */
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sysbus_mmio_map(s, 3, mem_base);
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d = FROM_SYSBUS(APBState, s);
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d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
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pci_apb_set_irq, pci_pbm_map_irq, pic,
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0, 32);
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pci_create_simple(d->host_state.bus, 0, "pbm");
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/* APB secondary busses */
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*bus2 = pci_bridge_init(d->host_state.bus, 8, PCI_VENDOR_ID_SUN,
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PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq,
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"Advanced PCI Bus secondary bridge 1");
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*bus3 = pci_bridge_init(d->host_state.bus, 9, PCI_VENDOR_ID_SUN,
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PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq,
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"Advanced PCI Bus secondary bridge 2");
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return d->host_state.bus;
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}
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static int pci_pbm_init_device(SysBusDevice *dev)
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{
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APBState *s;
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
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s = FROM_SYSBUS(APBState, dev);
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/* apb_config */
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apb_config = cpu_register_io_memory(apb_config_read,
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apb_config_write, s);
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sysbus_init_mmio(dev, 0x40ULL, apb_config);
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/* pci_ioport */
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pci_ioport = cpu_register_io_memory(pci_apb_ioread,
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pci_apb_iowrite, s);
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sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
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/* mem_config */
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pci_mem_config = cpu_register_io_memory(pci_apb_config_read,
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pci_apb_config_write, s);
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sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
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/* mem_data */
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pci_mem_data = cpu_register_io_memory(pci_apb_read,
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pci_apb_write, &s->host_state);
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sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
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return 0;
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}
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static int pbm_pci_host_init(PCIDevice *d)
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{
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
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d->config[0x04] = 0x06; // command = bus master, pci mem
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d->config[0x05] = 0x00;
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d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
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d->config[0x07] = 0x03; // status = medium devsel
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d->config[0x08] = 0x00; // revision
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d->config[0x09] = 0x00; // programming i/f
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
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d->config[0x0D] = 0x10; // latency_timer
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d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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return 0;
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}
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static PCIDeviceInfo pbm_pci_host_info = {
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.qdev.name = "pbm",
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.qdev.size = sizeof(PCIDevice),
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.init = pbm_pci_host_init,
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};
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static void pbm_register_devices(void)
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{
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sysbus_register_dev("pbm", sizeof(APBState), pci_pbm_init_device);
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pci_qdev_register(&pbm_pci_host_info);
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}
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device_init(pbm_register_devices)
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