db592b5b16
The interrupt modes supported by the hypervisor are advertised to the guest with new bits definitions of the option vector 5 of property "ibm,arch-vec-5-platform-support. The byte 23 bits 0-1 of the OV5 are defined as follow : 0b00 PAPR 2.7 and earlier (Legacy systems) 0b01 XIVE Exploitation mode only 0b10 Either available If the client/guest selects the XIVE interrupt mode, it informs the hypervisor by returning the value 0b01 in byte 23 bits 0-1. A 0b00 value indicates the use of the XICS interrupt mode (Legacy systems). The sPAPR IRQ backend is extended with these definitions and the values are directly used to populate the "ibm,arch-vec-5-platform-support" property. The interrupt mode is advertised under TCG and under KVM. Although a KVM XIVE device is not yet available, the machine can still operate with kernel_irqchip=off. However, we apply a restriction on the CPU which is required to be a POWER9 when a XIVE interrupt controller is in use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
69 lines
2.5 KiB
C
69 lines
2.5 KiB
C
/*
|
|
* QEMU PowerPC sPAPR IRQ backend definitions
|
|
*
|
|
* Copyright (c) 2018, IBM Corporation.
|
|
*
|
|
* This code is licensed under the GPL version 2 or later. See the
|
|
* COPYING file in the top-level directory.
|
|
*/
|
|
|
|
#ifndef HW_SPAPR_IRQ_H
|
|
#define HW_SPAPR_IRQ_H
|
|
|
|
/*
|
|
* IRQ range offsets per device type
|
|
*/
|
|
#define SPAPR_IRQ_IPI 0x0
|
|
#define SPAPR_IRQ_EPOW 0x1000 /* XICS_IRQ_BASE offset */
|
|
#define SPAPR_IRQ_HOTPLUG 0x1001
|
|
#define SPAPR_IRQ_VIO 0x1100 /* 256 VIO devices */
|
|
#define SPAPR_IRQ_PCI_LSI 0x1200 /* 32+ PHBs devices */
|
|
|
|
#define SPAPR_IRQ_MSI 0x1300 /* Offset of the dynamic range covered
|
|
* by the bitmap allocator */
|
|
|
|
typedef struct sPAPRMachineState sPAPRMachineState;
|
|
|
|
void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis);
|
|
int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
|
|
Error **errp);
|
|
void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num);
|
|
void spapr_irq_msi_reset(sPAPRMachineState *spapr);
|
|
|
|
typedef struct sPAPRIrq {
|
|
uint32_t nr_irqs;
|
|
uint32_t nr_msis;
|
|
uint8_t ov5;
|
|
|
|
void (*init)(sPAPRMachineState *spapr, Error **errp);
|
|
int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);
|
|
void (*free)(sPAPRMachineState *spapr, int irq, int num);
|
|
qemu_irq (*qirq)(sPAPRMachineState *spapr, int irq);
|
|
void (*print_info)(sPAPRMachineState *spapr, Monitor *mon);
|
|
void (*dt_populate)(sPAPRMachineState *spapr, uint32_t nr_servers,
|
|
void *fdt, uint32_t phandle);
|
|
Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu,
|
|
Error **errp);
|
|
int (*post_load)(sPAPRMachineState *spapr, int version_id);
|
|
void (*reset)(sPAPRMachineState *spapr, Error **errp);
|
|
} sPAPRIrq;
|
|
|
|
extern sPAPRIrq spapr_irq_xics;
|
|
extern sPAPRIrq spapr_irq_xics_legacy;
|
|
extern sPAPRIrq spapr_irq_xive;
|
|
|
|
void spapr_irq_init(sPAPRMachineState *spapr, Error **errp);
|
|
int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);
|
|
void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
|
|
qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
|
|
int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id);
|
|
void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp);
|
|
|
|
/*
|
|
* XICS legacy routines
|
|
*/
|
|
int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp);
|
|
#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
|
|
|
|
#endif
|