Alistair Francis ef63100648 hw/riscv: opentitan: Update to the latest build ...

Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com

2021-10-22 23:35:47 +10:00

..

boot.c

target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

2021-10-22 07:47:51 +10:00

Kconfig

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meson.build

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microchip_pfsoc.c

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numa.c

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opentitan.c

hw/riscv: opentitan: Update to the latest build

2021-10-22 23:35:47 +10:00

riscv_hart.c

…

shakti_c.c

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sifive_e.c

…

sifive_u.c

…

spike.c

…

virt.c

hw/riscv: virt: Use machine->ram as the system memory

2021-10-22 07:47:51 +10:00