adf772b0f7
Add trans_* and helper function for Zvfbfwma instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230615063302.102409-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
176 lines
5.6 KiB
C++
176 lines
5.6 KiB
C++
/*
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* RISC-V translation routines for the BF16 Standard Extensions.
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*
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* Copyright (c) 2020-2023 PLCT Lab
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_ZFBFMIN(ctx) do { \
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if (!ctx->cfg_ptr->ext_zfbfmin) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_ZVFBFMIN(ctx) do { \
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if (!ctx->cfg_ptr->ext_zvfbfmin) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_ZVFBFWMA(ctx) do { \
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if (!ctx->cfg_ptr->ext_zvfbfwma) { \
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return false; \
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} \
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} while (0)
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static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
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{
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REQUIRE_FPU;
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REQUIRE_ZFBFMIN(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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gen_set_rm(ctx, a->rm);
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gen_helper_fcvt_bf16_s(dest, cpu_env, src1);
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gen_set_fpr_hs(ctx, a->rd, dest);
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a)
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{
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REQUIRE_FPU;
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REQUIRE_ZFBFMIN(ctx);
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TCGv_i64 dest = dest_fpr(ctx, a->rd);
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TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
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gen_set_rm(ctx, a->rm);
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gen_helper_fcvt_s_bf16(dest, cpu_env, src1);
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gen_set_fpr_hs(ctx, a->rd, dest);
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mark_fs_dirty(ctx);
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return true;
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}
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static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
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{
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REQUIRE_FPU;
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REQUIRE_ZVFBFMIN(ctx);
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if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
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uint32_t data = 0;
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TCGLabel *over = gen_new_label();
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gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
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data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
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data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
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tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
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vreg_ofs(ctx, a->rs2), cpu_env,
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ctx->cfg_ptr->vlen / 8,
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ctx->cfg_ptr->vlen / 8, data,
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gen_helper_vfncvtbf16_f_f_w);
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mark_vs_dirty(ctx);
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gen_set_label(over);
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return true;
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}
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return false;
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}
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static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
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{
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REQUIRE_FPU;
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REQUIRE_ZVFBFMIN(ctx);
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if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
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uint32_t data = 0;
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TCGLabel *over = gen_new_label();
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gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
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data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
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data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
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tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
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vreg_ofs(ctx, a->rs2), cpu_env,
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ctx->cfg_ptr->vlen / 8,
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ctx->cfg_ptr->vlen / 8, data,
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gen_helper_vfwcvtbf16_f_f_v);
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mark_vs_dirty(ctx);
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gen_set_label(over);
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return true;
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}
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return false;
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}
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static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
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{
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REQUIRE_FPU;
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REQUIRE_ZVFBFWMA(ctx);
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if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
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vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
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uint32_t data = 0;
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TCGLabel *over = gen_new_label();
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gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
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tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
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data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
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data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
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tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
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vreg_ofs(ctx, a->rs1),
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vreg_ofs(ctx, a->rs2), cpu_env,
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ctx->cfg_ptr->vlen / 8,
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ctx->cfg_ptr->vlen / 8, data,
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gen_helper_vfwmaccbf16_vv);
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mark_vs_dirty(ctx);
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gen_set_label(over);
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return true;
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}
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return false;
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}
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static bool trans_vfwmaccbf16_vf(DisasContext *ctx, arg_vfwmaccbf16_vf *a)
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{
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REQUIRE_FPU;
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REQUIRE_ZVFBFWMA(ctx);
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if (require_rvv(ctx) && (ctx->sew == MO_16) && vext_check_isa_ill(ctx) &&
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vext_check_ds(ctx, a->rd, a->rs2, a->vm)) {
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uint32_t data = 0;
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gen_set_rm(ctx, RISCV_FRM_DYN);
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
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data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
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data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
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return opfvf_trans(a->rd, a->rs1, a->rs2, data,
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gen_helper_vfwmaccbf16_vf, ctx);
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}
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return false;
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}
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