a59a293126
With sparc64 we need not distinguish between registers that can hold 32-bit values and those that can hold 64-bit values. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23 lines
543 B
C
23 lines
543 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define Sparc target-specific constraint sets.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
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* Each operand should be a sequence of constraint letters as defined by
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I1(r)
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C_O0_I2(rZ, r)
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C_O0_I2(rZ, rJ)
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C_O0_I2(sZ, s)
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C_O1_I1(r, s)
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C_O1_I1(r, r)
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C_O1_I2(r, r, r)
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C_O1_I2(r, rZ, rJ)
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C_O1_I4(r, rZ, rJ, rI, 0)
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C_O2_I2(r, r, rZ, rJ)
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C_O2_I4(r, r, rZ, rZ, rJ, rJ)
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