qemu/hw/riscv
Sunil V L 4263e270a2 hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
Currently, virt machine supports two pflash instances each with
32MB size. However, the first pflash is always assumed to
contain M-mode firmware and reset vector is set to this if
enabled. Hence, for S-mode payloads like EDK2, only one pflash
instance is available for use. This means both code and NV variables
of EDK2 will need to use the same pflash.

The OS distros keep the EDK2 FW code as readonly. When non-volatile
variables also need to share the same pflash, it is not possible
to keep it as readonly since variables need write access.

To resolve this issue, the code and NV variables need to be separated.
But in that case we need an extra flash. Hence, modify the convention
for non-KVM guests such that, pflash0 will contain the M-mode FW
only when "-bios none" option is used. Otherwise, pflash0 will contain
the S-mode payload FW. This enables both pflash instances available
for EDK2 use.

When KVM is enabled, pflash0 is always assumed to contain the
S-mode payload firmware only.

Example usage:
1) pflash0 containing M-mode FW
qemu-system-riscv64 -bios none -pflash <mmode_fw> -machine virt
or
qemu-system-riscv64 -bios none \
-drive file=<mmode_fw>,if=pflash,format=raw,unit=0 -machine virt

2) pflash0 containing S-mode payload like EDK2
qemu-system-riscv64 -pflash <smode_fw_code> -pflash <smode_vars> -machine  virt
or
qemu-system-riscv64 -bios <opensbi_fw> \
-pflash <smode_fw_code> \
-pflash <smode_vars> \
-machine  virt
or
qemu-system-riscv64 -bios <opensbi_fw> \
-drive file=<smode_fw_code>,if=pflash,format=raw,unit=0,readonly=on \
-drive file=<smode_fw_vars>,if=pflash,format=raw,unit=1 \
-machine virt

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230601045910.18646-2-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13 17:38:56 +10:00
..
boot.c hw/riscv/boot.c: make riscv_load_initrd() static 2023-02-16 07:55:37 -08:00
Kconfig hw/riscv/virt: Enable basic ACPI infrastructure 2023-03-06 11:35:04 -08:00
meson.build hw/riscv/virt: Enable basic ACPI infrastructure 2023-03-06 11:35:04 -08:00
microchip_pfsoc.c hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() 2023-02-16 07:55:30 -08:00
numa.c hw/riscv: qemu crash when NUMA nodes exceed available CPUs 2023-06-13 17:20:31 +10:00
opentitan.c hw/riscv/opentitan: Correct OpenTitanState parent type/size 2023-06-13 17:19:42 +10:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c *: Add missing includes of qemu/error-report.h 2023-03-22 15:06:57 +00:00
sifive_e.c hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() 2023-02-16 07:55:30 -08:00
sifive_u.c hw/riscv: Move the dtb load bits outside of create_fdt() 2023-03-01 17:19:14 -08:00
spike.c hw/riscv: Add signature dump function for spike to run ACT tests 2023-05-05 10:49:50 +10:00
virt-acpi-build.c *: Add missing includes of qemu/error-report.h 2023-03-22 15:06:57 +00:00
virt.c hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" 2023-06-13 17:38:56 +10:00