468 lines
14 KiB
C
468 lines
14 KiB
C
/*
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* Virtual hardware watchdog.
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*
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* Copyright (C) 2009 Red Hat Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* By Richard W.M. Jones (rjones@redhat.com).
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*/
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#include <inttypes.h>
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#include "qemu-common.h"
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#include "qemu-timer.h"
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#include "watchdog.h"
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#include "hw.h"
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#include "pci.h"
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/*#define I6300ESB_DEBUG 1*/
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#ifdef I6300ESB_DEBUG
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#define i6300esb_debug(fs,...) \
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fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
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#else
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#define i6300esb_debug(fs,...)
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#endif
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#ifndef PCI_DEVICE_ID_INTEL_ESB_9
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#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
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#endif
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/* PCI configuration registers */
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#define ESB_CONFIG_REG 0x60 /* Config register */
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#define ESB_LOCK_REG 0x68 /* WDT lock register */
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/* Memory mapped registers (offset from base address) */
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#define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
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#define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
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#define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
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#define ESB_RELOAD_REG 0x0c /* Reload register */
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/* Lock register bits */
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#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
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#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
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#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
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/* Config register bits */
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#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
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#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
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#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
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/* Reload register bits */
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#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
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/* Magic constants */
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#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
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#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
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/* Device state. */
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struct I6300State {
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PCIDevice dev;
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int reboot_enabled; /* "Reboot" on timer expiry. The real action
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* performed depends on the -watchdog-action
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* param passed on QEMU command line.
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*/
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int clock_scale; /* Clock scale. */
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#define CLOCK_SCALE_1KHZ 0
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#define CLOCK_SCALE_1MHZ 1
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int int_type; /* Interrupt type generated. */
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#define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */
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#define INT_TYPE_SMI 2
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#define INT_TYPE_DISABLED 3
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int free_run; /* If true, reload timer on expiry. */
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int locked; /* If true, enabled field cannot be changed. */
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int enabled; /* If true, watchdog is enabled. */
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QEMUTimer *timer; /* The actual watchdog timer. */
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uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */
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uint32_t timer2_preload;
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int stage; /* Stage (1 or 2). */
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int unlock_state; /* Guest writes 0x80, 0x86 to unlock the
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* registers, and we transition through
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* states 0 -> 1 -> 2 when this happens.
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*/
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int previous_reboot_flag; /* If the watchdog caused the previous
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* reboot, this flag will be set.
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*/
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};
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typedef struct I6300State I6300State;
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/* This function is called when the watchdog has either been enabled
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* (hence it starts counting down) or has been keep-alived.
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*/
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static void i6300esb_restart_timer(I6300State *d, int stage)
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{
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int64_t timeout;
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if (!d->enabled)
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return;
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d->stage = stage;
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if (d->stage <= 1)
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timeout = d->timer1_preload;
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else
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timeout = d->timer2_preload;
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if (d->clock_scale == CLOCK_SCALE_1KHZ)
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timeout <<= 15;
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else
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timeout <<= 5;
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/* Get the timeout in units of ticks_per_sec. */
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timeout = get_ticks_per_sec() * timeout / 33000000;
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i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
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qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout);
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}
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/* This is called when the guest disables the watchdog. */
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static void i6300esb_disable_timer(I6300State *d)
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{
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i6300esb_debug("timer disabled\n");
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qemu_del_timer(d->timer);
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}
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static void i6300esb_reset(I6300State *d)
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{
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/* XXX We should probably reset other parts of the state here,
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* but we should also reset our state on general machine reset
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* too. For now just disable the timer so it doesn't fire
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* again after the reboot.
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*/
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i6300esb_disable_timer(d);
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}
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/* This function is called when the watchdog expires. Note that
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* the hardware has two timers, and so expiry happens in two stages.
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* If d->stage == 1 then we perform the first stage action (usually,
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* sending an interrupt) and then restart the timer again for the
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* second stage. If the second stage expires then the watchdog
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* really has run out.
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*/
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static void i6300esb_timer_expired(void *vp)
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{
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I6300State *d = (I6300State *) vp;
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i6300esb_debug("stage %d\n", d->stage);
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if (d->stage == 1) {
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/* What to do at the end of stage 1? */
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switch (d->int_type) {
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case INT_TYPE_IRQ:
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fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
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break;
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case INT_TYPE_SMI:
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fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
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break;
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}
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/* Start the second stage. */
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i6300esb_restart_timer(d, 2);
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} else {
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/* Second stage expired, reboot for real. */
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if (d->reboot_enabled) {
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d->previous_reboot_flag = 1;
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watchdog_perform_action(); /* This reboots, exits, etc */
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i6300esb_reset(d);
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}
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/* In "free running mode" we start stage 1 again. */
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if (d->free_run)
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i6300esb_restart_timer(d, 1);
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}
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}
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static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
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uint32_t data, int len)
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{
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I6300State *d = DO_UPCAST(I6300State, dev, dev);
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int old;
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i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
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if (addr == ESB_CONFIG_REG && len == 2) {
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d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
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d->clock_scale =
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(data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
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d->int_type = (data & ESB_WDT_INTTYPE);
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} else if (addr == ESB_LOCK_REG && len == 1) {
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if (!d->locked) {
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d->locked = (data & ESB_WDT_LOCK) != 0;
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d->free_run = (data & ESB_WDT_FUNC) != 0;
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old = d->enabled;
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d->enabled = (data & ESB_WDT_ENABLE) != 0;
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if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
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i6300esb_restart_timer(d, 1);
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else if (!d->enabled)
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i6300esb_disable_timer(d);
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}
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} else {
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pci_default_write_config(dev, addr, data, len);
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}
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}
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static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
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{
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I6300State *d = DO_UPCAST(I6300State, dev, dev);
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uint32_t data;
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i6300esb_debug ("addr = %x, len = %d\n", addr, len);
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if (addr == ESB_CONFIG_REG && len == 2) {
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data =
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(d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
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(d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
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d->int_type;
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return data;
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} else if (addr == ESB_LOCK_REG && len == 1) {
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data =
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(d->free_run ? ESB_WDT_FUNC : 0) |
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(d->locked ? ESB_WDT_LOCK : 0) |
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(d->enabled ? ESB_WDT_ENABLE : 0);
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return data;
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} else {
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return pci_default_read_config(dev, addr, len);
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}
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}
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static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
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{
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i6300esb_debug ("addr = %x\n", (int) addr);
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return 0;
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}
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static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
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{
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uint32_t data = 0;
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I6300State *d = (I6300State *) vp;
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i6300esb_debug("addr = %x\n", (int) addr);
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if (addr == 0xc) {
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/* The previous reboot flag is really bit 9, but there is
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* a bug in the Linux driver where it thinks it's bit 12.
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* Set both.
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*/
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data = d->previous_reboot_flag ? 0x1200 : 0;
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}
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return data;
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}
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static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
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{
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i6300esb_debug("addr = %x\n", (int) addr);
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return 0;
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}
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static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
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{
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I6300State *d = (I6300State *) vp;
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i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
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if (addr == 0xc && val == 0x80)
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d->unlock_state = 1;
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else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
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d->unlock_state = 2;
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}
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static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
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{
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I6300State *d = (I6300State *) vp;
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i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
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if (addr == 0xc && val == 0x80)
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d->unlock_state = 1;
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else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
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d->unlock_state = 2;
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else {
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if (d->unlock_state == 2) {
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if (addr == 0xc) {
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if ((val & 0x100) != 0)
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/* This is the "ping" from the userspace watchdog in
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* the guest ...
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*/
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i6300esb_restart_timer(d, 1);
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/* Setting bit 9 resets the previous reboot flag.
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* There's a bug in the Linux driver where it sets
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* bit 12 instead.
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*/
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if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
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d->previous_reboot_flag = 0;
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}
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}
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d->unlock_state = 0;
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}
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}
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}
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static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
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{
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I6300State *d = (I6300State *) vp;
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i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
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if (addr == 0xc && val == 0x80)
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d->unlock_state = 1;
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else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
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d->unlock_state = 2;
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else {
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if (d->unlock_state == 2) {
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if (addr == 0)
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d->timer1_preload = val & 0xfffff;
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else if (addr == 4)
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d->timer2_preload = val & 0xfffff;
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d->unlock_state = 0;
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}
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}
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}
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static void i6300esb_map(PCIDevice *dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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static CPUReadMemoryFunc * const mem_read[3] = {
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i6300esb_mem_readb,
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i6300esb_mem_readw,
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i6300esb_mem_readl,
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};
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static CPUWriteMemoryFunc * const mem_write[3] = {
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i6300esb_mem_writeb,
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i6300esb_mem_writew,
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i6300esb_mem_writel,
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};
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I6300State *d = DO_UPCAST(I6300State, dev, dev);
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int io_mem;
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i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type);
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io_mem = cpu_register_io_memory(mem_read, mem_write, d);
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cpu_register_physical_memory (addr, 0x10, io_mem);
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/* qemu_register_coalesced_mmio (addr, 0x10); ? */
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}
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static void i6300esb_save(QEMUFile *f, void *vp)
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{
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I6300State *d = (I6300State *) vp;
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pci_device_save(&d->dev, f);
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qemu_put_be32(f, d->reboot_enabled);
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qemu_put_be32(f, d->clock_scale);
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qemu_put_be32(f, d->int_type);
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qemu_put_be32(f, d->free_run);
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qemu_put_be32(f, d->locked);
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qemu_put_be32(f, d->enabled);
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qemu_put_timer(f, d->timer);
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qemu_put_be32(f, d->timer1_preload);
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qemu_put_be32(f, d->timer2_preload);
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qemu_put_be32(f, d->stage);
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qemu_put_be32(f, d->unlock_state);
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qemu_put_be32(f, d->previous_reboot_flag);
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}
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static int i6300esb_load(QEMUFile *f, void *vp, int version)
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{
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I6300State *d = (I6300State *) vp;
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if (version != sizeof (I6300State))
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return -EINVAL;
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pci_device_load(&d->dev, f);
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d->reboot_enabled = qemu_get_be32(f);
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d->clock_scale = qemu_get_be32(f);
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d->int_type = qemu_get_be32(f);
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d->free_run = qemu_get_be32(f);
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d->locked = qemu_get_be32(f);
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d->enabled = qemu_get_be32(f);
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qemu_get_timer(f, d->timer);
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d->timer1_preload = qemu_get_be32(f);
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d->timer2_preload = qemu_get_be32(f);
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d->stage = qemu_get_be32(f);
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d->unlock_state = qemu_get_be32(f);
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d->previous_reboot_flag = qemu_get_be32(f);
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return 0;
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}
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static int i6300esb_init(PCIDevice *dev)
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{
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I6300State *d = DO_UPCAST(I6300State, dev, dev);
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uint8_t *pci_conf;
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d->reboot_enabled = 1;
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d->clock_scale = CLOCK_SCALE_1KHZ;
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d->int_type = INT_TYPE_IRQ;
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d->free_run = 0;
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d->locked = 0;
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d->enabled = 0;
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d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d);
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d->timer1_preload = 0xfffff;
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d->timer2_preload = 0xfffff;
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d->stage = 1;
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d->unlock_state = 0;
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d->previous_reboot_flag = 0;
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pci_conf = d->dev.config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9);
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pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER);
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pci_conf[0x0e] = 0x00;
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pci_register_bar(&d->dev, 0, 0x10,
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PCI_ADDRESS_SPACE_MEM, i6300esb_map);
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register_savevm("i6300esb_wdt", -1, sizeof(I6300State),
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i6300esb_save, i6300esb_load, d);
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return 0;
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}
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static WatchdogTimerModel model = {
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.wdt_name = "i6300esb",
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.wdt_description = "Intel 6300ESB",
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};
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static PCIDeviceInfo i6300esb_info = {
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.qdev.name = "i6300esb",
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.qdev.size = sizeof(I6300State),
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.config_read = i6300esb_config_read,
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.config_write = i6300esb_config_write,
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.init = i6300esb_init,
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};
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static void i6300esb_register_devices(void)
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{
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watchdog_add_model(&model);
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pci_qdev_register(&i6300esb_info);
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}
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device_init(i6300esb_register_devices);
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