Jiaxun Yang 2a2105a262 target/mips: Don't check COP1X for 64 bit FP mode ... Some implementations (i.e. Loongson-2F) may decide to implement a 64 bit FPU without implementing COP1X instructions. As the eligibility of 64 bit FP instructions is already determined by CP0St_FR, there is no need to check for COP1X again. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221102165719.190378-1-jiaxun.yang@flygoat.com> [PMD: Add missing trailing parenthesis (buildfix)] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2022-11-08 01:04:25 +01:00
..
sysemu
tcg	target/mips: Don't check COP1X for 64 bit FP mode	2022-11-08 01:04:25 +01:00
cpu-defs.c.inc	target/mips: Disable DSP ASE for Octeon68XX	2022-11-08 01:04:25 +01:00
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu-qom.h
cpu.c	target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F	2022-11-08 01:04:25 +01:00
cpu.h	target/mips: Use an exception for semihosting	2022-06-28 10:13:42 +05:30
fpu_helper.h
fpu.c
gdbstub.c
helper.h
internal.h	MIPS patches queue	2022-03-09 09:13:39 +00:00
Kconfig
kvm_mips.h
kvm.c	kvm: allow target-specific accelerator properties	2022-10-10 09:23:16 +02:00
meson.build
mips-defs.h	target/mips: introduce decodetree structure for Cavium Octeon extension	2022-07-12 22:30:09 +02:00
msa.c