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qemu/target/riscv/insn_trans
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LIU Zhiwei 40f0c2046c target/riscv: Sign extend pc for different XLEN 
When pc is written, it is sign-extended to fill the widest supported XLEN.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21 15:52:57 +10:00
..
trans_privileged.c.inc
target/riscv: Sign extend pc for different XLEN
2022-01-21 15:52:57 +10:00
trans_rva.c.inc
exec/memop: Adding signedness to quad definitions
2022-01-08 15:46:10 +10:00
trans_rvb.c.inc
target/riscv: support for 128-bit arithmetic instructions
2022-01-08 15:46:10 +10:00
trans_rvd.c.inc
exec/memop: Adding signedness to quad definitions
2022-01-08 15:46:10 +10:00
trans_rvf.c.inc
…
trans_rvh.c.inc
exec/memop: Adding signedness to quad definitions
2022-01-08 15:46:10 +10:00
trans_rvi.c.inc
target/riscv: Sign extend pc for different XLEN
2022-01-21 15:52:57 +10:00
trans_rvm.c.inc
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
trans_rvv.c.inc
target/riscv: Sign extend pc for different XLEN
2022-01-21 15:52:57 +10:00
trans_rvzfh.c.inc
…