acae6f1c4c
With the conversion of the block layer to coroutines, bdrv_read/write have changed to run a nested event loop that calls qemu_bh_poll. Consequently a scheduled BH can be called while a DMA transfer handler runs and this means that DMA_run becomes reentrant. Devices haven't been designed to cope with that, so instead of running a nested transfer handler just wait for the next invocation of the BH from the main loop. This fixes some problems with the floppy device. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
566 lines
14 KiB
C
566 lines
14 KiB
C
/*
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* QEMU DMA emulation
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*
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* Copyright (c) 2003-2004 Vassili Karpov (malc)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "isa.h"
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/* #define DEBUG_DMA */
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#define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
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#ifdef DEBUG_DMA
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#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
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#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
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#else
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#define linfo(...)
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#define ldebug(...)
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#endif
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struct dma_regs {
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int now[2];
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uint16_t base[2];
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uint8_t mode;
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uint8_t page;
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uint8_t pageh;
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uint8_t dack;
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uint8_t eop;
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DMA_transfer_handler transfer_handler;
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void *opaque;
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};
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#define ADDR 0
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#define COUNT 1
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static struct dma_cont {
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uint8_t status;
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uint8_t command;
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uint8_t mask;
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uint8_t flip_flop;
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int dshift;
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struct dma_regs regs[4];
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qemu_irq *cpu_request_exit;
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} dma_controllers[2];
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enum {
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CMD_MEMORY_TO_MEMORY = 0x01,
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CMD_FIXED_ADDRESS = 0x02,
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CMD_BLOCK_CONTROLLER = 0x04,
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CMD_COMPRESSED_TIME = 0x08,
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CMD_CYCLIC_PRIORITY = 0x10,
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CMD_EXTENDED_WRITE = 0x20,
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CMD_LOW_DREQ = 0x40,
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CMD_LOW_DACK = 0x80,
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CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
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| CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
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| CMD_LOW_DREQ | CMD_LOW_DACK
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};
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static void DMA_run (void);
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static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
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static void write_page (void *opaque, uint32_t nport, uint32_t data)
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{
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struct dma_cont *d = opaque;
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int ichan;
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ichan = channels[nport & 7];
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if (-1 == ichan) {
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dolog ("invalid channel %#x %#x\n", nport, data);
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return;
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}
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d->regs[ichan].page = data;
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}
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static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
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{
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struct dma_cont *d = opaque;
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int ichan;
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ichan = channels[nport & 7];
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if (-1 == ichan) {
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dolog ("invalid channel %#x %#x\n", nport, data);
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return;
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}
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d->regs[ichan].pageh = data;
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}
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static uint32_t read_page (void *opaque, uint32_t nport)
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{
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struct dma_cont *d = opaque;
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int ichan;
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ichan = channels[nport & 7];
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if (-1 == ichan) {
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dolog ("invalid channel read %#x\n", nport);
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return 0;
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}
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return d->regs[ichan].page;
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}
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static uint32_t read_pageh (void *opaque, uint32_t nport)
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{
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struct dma_cont *d = opaque;
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int ichan;
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ichan = channels[nport & 7];
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if (-1 == ichan) {
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dolog ("invalid channel read %#x\n", nport);
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return 0;
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}
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return d->regs[ichan].pageh;
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}
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static inline void init_chan (struct dma_cont *d, int ichan)
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{
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struct dma_regs *r;
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r = d->regs + ichan;
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r->now[ADDR] = r->base[ADDR] << d->dshift;
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r->now[COUNT] = 0;
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}
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static inline int getff (struct dma_cont *d)
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{
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int ff;
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ff = d->flip_flop;
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d->flip_flop = !ff;
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return ff;
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}
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static uint32_t read_chan (void *opaque, uint32_t nport)
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{
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struct dma_cont *d = opaque;
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int ichan, nreg, iport, ff, val, dir;
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struct dma_regs *r;
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iport = (nport >> d->dshift) & 0x0f;
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ichan = iport >> 1;
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nreg = iport & 1;
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r = d->regs + ichan;
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dir = ((r->mode >> 5) & 1) ? -1 : 1;
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ff = getff (d);
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if (nreg)
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val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
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else
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val = r->now[ADDR] + r->now[COUNT] * dir;
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ldebug ("read_chan %#x -> %d\n", iport, val);
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return (val >> (d->dshift + (ff << 3))) & 0xff;
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}
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static void write_chan (void *opaque, uint32_t nport, uint32_t data)
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{
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struct dma_cont *d = opaque;
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int iport, ichan, nreg;
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struct dma_regs *r;
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iport = (nport >> d->dshift) & 0x0f;
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ichan = iport >> 1;
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nreg = iport & 1;
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r = d->regs + ichan;
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if (getff (d)) {
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r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
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init_chan (d, ichan);
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} else {
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r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
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}
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}
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static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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{
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struct dma_cont *d = opaque;
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int iport, ichan = 0;
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iport = (nport >> d->dshift) & 0x0f;
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switch (iport) {
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case 0x08: /* command */
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if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
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dolog ("command %#x not supported\n", data);
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return;
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}
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d->command = data;
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break;
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case 0x09:
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ichan = data & 3;
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if (data & 4) {
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d->status |= 1 << (ichan + 4);
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}
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else {
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d->status &= ~(1 << (ichan + 4));
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}
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d->status &= ~(1 << ichan);
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DMA_run();
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break;
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case 0x0a: /* single mask */
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if (data & 4)
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d->mask |= 1 << (data & 3);
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else
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d->mask &= ~(1 << (data & 3));
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DMA_run();
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break;
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case 0x0b: /* mode */
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{
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ichan = data & 3;
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#ifdef DEBUG_DMA
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{
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int op, ai, dir, opmode;
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op = (data >> 2) & 3;
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ai = (data >> 4) & 1;
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dir = (data >> 5) & 1;
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opmode = (data >> 6) & 3;
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linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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ichan, op, ai, dir, opmode);
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}
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#endif
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d->regs[ichan].mode = data;
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break;
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}
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case 0x0c: /* clear flip flop */
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d->flip_flop = 0;
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break;
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case 0x0d: /* reset */
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d->flip_flop = 0;
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d->mask = ~0;
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d->status = 0;
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d->command = 0;
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break;
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case 0x0e: /* clear mask for all channels */
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d->mask = 0;
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DMA_run();
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break;
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case 0x0f: /* write mask for all channels */
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d->mask = data;
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DMA_run();
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break;
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default:
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dolog ("unknown iport %#x\n", iport);
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break;
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}
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#ifdef DEBUG_DMA
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if (0xc != iport) {
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linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
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nport, ichan, data);
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}
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#endif
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}
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static uint32_t read_cont (void *opaque, uint32_t nport)
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{
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struct dma_cont *d = opaque;
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int iport, val;
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iport = (nport >> d->dshift) & 0x0f;
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switch (iport) {
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case 0x08: /* status */
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val = d->status;
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d->status &= 0xf0;
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break;
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case 0x0f: /* mask */
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val = d->mask;
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break;
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default:
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val = 0;
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break;
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}
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ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
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return val;
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}
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int DMA_get_channel_mode (int nchan)
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{
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return dma_controllers[nchan > 3].regs[nchan & 3].mode;
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}
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void DMA_hold_DREQ (int nchan)
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{
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int ncont, ichan;
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ncont = nchan > 3;
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ichan = nchan & 3;
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linfo ("held cont=%d chan=%d\n", ncont, ichan);
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dma_controllers[ncont].status |= 1 << (ichan + 4);
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DMA_run();
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}
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void DMA_release_DREQ (int nchan)
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{
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int ncont, ichan;
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ncont = nchan > 3;
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ichan = nchan & 3;
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linfo ("released cont=%d chan=%d\n", ncont, ichan);
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dma_controllers[ncont].status &= ~(1 << (ichan + 4));
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DMA_run();
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}
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static void channel_run (int ncont, int ichan)
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{
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int n;
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struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
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#ifdef DEBUG_DMA
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int dir, opmode;
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dir = (r->mode >> 5) & 1;
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opmode = (r->mode >> 6) & 3;
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if (dir) {
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dolog ("DMA in address decrement mode\n");
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}
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if (opmode != 1) {
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dolog ("DMA not in single mode select %#x\n", opmode);
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}
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#endif
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n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
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r->now[COUNT], (r->base[COUNT] + 1) << ncont);
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r->now[COUNT] = n;
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ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
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}
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static QEMUBH *dma_bh;
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static void DMA_run (void)
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{
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struct dma_cont *d;
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int icont, ichan;
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int rearm = 0;
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static int running = 0;
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if (running) {
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rearm = 1;
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goto out;
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} else {
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running = 1;
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}
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d = dma_controllers;
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for (icont = 0; icont < 2; icont++, d++) {
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for (ichan = 0; ichan < 4; ichan++) {
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int mask;
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mask = 1 << ichan;
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if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
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channel_run (icont, ichan);
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rearm = 1;
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}
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}
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}
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running = 0;
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out:
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if (rearm)
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qemu_bh_schedule_idle(dma_bh);
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}
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static void DMA_run_bh(void *unused)
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{
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DMA_run();
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}
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void DMA_register_channel (int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque)
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{
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struct dma_regs *r;
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int ichan, ncont;
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ncont = nchan > 3;
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ichan = nchan & 3;
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r = dma_controllers[ncont].regs + ichan;
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r->transfer_handler = transfer_handler;
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r->opaque = opaque;
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}
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int DMA_read_memory (int nchan, void *buf, int pos, int len)
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{
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struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
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target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
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if (r->mode & 0x20) {
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int i;
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uint8_t *p = buf;
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cpu_physical_memory_read (addr - pos - len, buf, len);
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/* What about 16bit transfers? */
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for (i = 0; i < len >> 1; i++) {
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uint8_t b = p[len - i - 1];
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p[i] = b;
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}
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}
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else
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cpu_physical_memory_read (addr + pos, buf, len);
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return len;
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}
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int DMA_write_memory (int nchan, void *buf, int pos, int len)
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{
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struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
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target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
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if (r->mode & 0x20) {
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int i;
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uint8_t *p = buf;
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cpu_physical_memory_write (addr - pos - len, buf, len);
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/* What about 16bit transfers? */
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for (i = 0; i < len; i++) {
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uint8_t b = p[len - i - 1];
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p[i] = b;
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}
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}
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else
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cpu_physical_memory_write (addr + pos, buf, len);
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return len;
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}
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/* request the emulator to transfer a new DMA memory block ASAP */
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void DMA_schedule(int nchan)
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{
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struct dma_cont *d = &dma_controllers[nchan > 3];
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qemu_irq_pulse(*d->cpu_request_exit);
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}
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static void dma_reset(void *opaque)
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{
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struct dma_cont *d = opaque;
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write_cont (d, (0x0d << d->dshift), 0);
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}
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static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len)
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{
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dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
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nchan, dma_pos, dma_len);
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return dma_pos;
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}
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|
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/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
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static void dma_init2(struct dma_cont *d, int base, int dshift,
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int page_base, int pageh_base,
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qemu_irq *cpu_request_exit)
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{
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static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
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int i;
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d->dshift = dshift;
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d->cpu_request_exit = cpu_request_exit;
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for (i = 0; i < 8; i++) {
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register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
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register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
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}
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for (i = 0; i < ARRAY_SIZE (page_port_list); i++) {
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register_ioport_write (page_base + page_port_list[i], 1, 1,
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write_page, d);
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register_ioport_read (page_base + page_port_list[i], 1, 1,
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read_page, d);
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if (pageh_base >= 0) {
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register_ioport_write (pageh_base + page_port_list[i], 1, 1,
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write_pageh, d);
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register_ioport_read (pageh_base + page_port_list[i], 1, 1,
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read_pageh, d);
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}
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}
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for (i = 0; i < 8; i++) {
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register_ioport_write (base + ((i + 8) << dshift), 1, 1,
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write_cont, d);
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register_ioport_read (base + ((i + 8) << dshift), 1, 1,
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read_cont, d);
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}
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qemu_register_reset(dma_reset, d);
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dma_reset(d);
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for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
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d->regs[i].transfer_handler = dma_phony_handler;
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}
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}
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|
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static const VMStateDescription vmstate_dma_regs = {
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.name = "dma_regs",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
|
|
VMSTATE_INT32_ARRAY(now, struct dma_regs, 2),
|
|
VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2),
|
|
VMSTATE_UINT8(mode, struct dma_regs),
|
|
VMSTATE_UINT8(page, struct dma_regs),
|
|
VMSTATE_UINT8(pageh, struct dma_regs),
|
|
VMSTATE_UINT8(dack, struct dma_regs),
|
|
VMSTATE_UINT8(eop, struct dma_regs),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static int dma_post_load(void *opaque, int version_id)
|
|
{
|
|
DMA_run();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_dma = {
|
|
.name = "dma",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.post_load = dma_post_load,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_UINT8(command, struct dma_cont),
|
|
VMSTATE_UINT8(mask, struct dma_cont),
|
|
VMSTATE_UINT8(flip_flop, struct dma_cont),
|
|
VMSTATE_INT32(dshift, struct dma_cont),
|
|
VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
|
|
{
|
|
dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
|
|
high_page_enable ? 0x480 : -1, cpu_request_exit);
|
|
dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
|
|
high_page_enable ? 0x488 : -1, cpu_request_exit);
|
|
vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]);
|
|
vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]);
|
|
|
|
dma_bh = qemu_bh_new(DMA_run_bh, NULL);
|
|
}
|