qemu/target
Peter Maydell f6c98f91f5 target/arm: Remove can't-happen if() from handle_vec_simd_shli()
In handle_vec_simd_shli() we have a check:
     if (size > 3 && !is_q) {
         unallocated_encoding(s);
         return;
     }
However this can never be true, because we calculate
    int size = 32 - clz32(immh) - 1;
where immh is a 4 bit field which we know cannot be all-zeroes.
So the clz32() return must be in {28,29,30,31} and the resulting
size is in {0,1,2,3}, and "size > 3" is never true.

This unnecessary code confuses Coverity's analysis:
in CID 1396476 it thinks we might later index off the
end of an array because the condition implies that we
might have a size > 3.

Remove the code, and instead assert that the size is in [0..3],
since the decode that enforces that is somewhat distant from
this function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20181030162517.21816-1-peter.maydell@linaro.org
2018-11-06 11:32:13 +00:00
..
alpha target/alpha: remove tlb_flush from alpha_cpu_initfn 2018-10-18 18:58:10 -07:00
arm target/arm: Remove can't-happen if() from handle_vec_simd_shli() 2018-11-06 11:32:13 +00:00
cris target/cris/translate: Get rid of qemu_log_separate() 2018-10-16 17:57:23 +02:00
hppa target/hppa: Raise exception 26 on emulated hardware 2018-10-16 15:32:22 -07:00
i386 i386: Add PKU on Skylake-Server CPU model 2018-10-30 21:14:43 -03:00
lm32 tcg-next queue 2018-06-04 11:28:31 +01:00
m68k target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTED 2018-11-01 12:12:24 +01:00
microblaze target-microblaze: Rework NOP/zero instruction handling 2018-06-15 09:05:00 +02:00
mips target/mips: Amend MXU ASE overview note 2018-10-29 14:13:59 +01:00
moxie tcg-next queue 2018-06-04 11:28:31 +01:00
nios2 tcg-next queue 2018-06-04 11:28:31 +01:00
openrisc decodetree: Remove "insn" argument from trans_* expanders 2018-10-31 16:48:54 +00:00
ppc Error reporting patches for 2018-10-22 2018-10-23 17:20:23 +01:00
riscv target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 2018-10-30 11:04:28 -07:00
s390x target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate 2018-10-18 19:46:53 -07:00
sh4 sh4: fix use_icount with linux-user 2018-08-20 00:11:06 +02:00
sparc SPARC64: add icount support 2018-06-17 11:13:06 +01:00
tilegx tcg-next queue 2018-06-04 11:28:31 +01:00
tricore tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
unicore32 target/unicore32: remove tlb_flush from uc32_init_fn 2018-10-18 18:58:10 -07:00
xtensa target/xtensa: extract gen_check_interrupts call 2018-10-01 11:08:36 -07:00