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Peter Maydell 3f37979bf5 arm: tcg: Adhere to SMCCC 1.3 section 5.2 
The SMCCC 1.3 spec section 5.2 says

  The Unknown SMC Function Identifier is a sign-extended value of (-1)
  that is returned in the R0, W0 or X0 registers. An implementation must
  return this error code when it receives:

    * An SMC or HVC call with an unknown Function Identifier
    * An SMC or HVC call for a removed Function Identifier
    * An SMC64/HVC64 call from AArch32 state

To comply with these statements, let's always return -1 when we encounter
an unknown HVC or SMC call.

[PMM:
 This is a reinstatement of commit 9fcd15b919, previously
 reverted in commit 4825eaae4fdd56fba0f; we can do this now that we
 have arranged for all the affected board models to not enable the
 PSCI emulation if they are running guest code at EL3. This avoids
 the regressions that caused us to revert the change for 7.0.]

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-08 10:56:28 +00:00
..
hvf hvf: arm: Ignore cache operations on MMIO 2021-11-02 14:18:33 -04:00
a32-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
a32.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arch_dump.c target/arm: add spaces around operator 2020-11-10 11:03:47 +00:00
arm_ldst.h accel/tcg: Add DisasContextBase argument to translator_ld* 2021-09-14 12:00:20 -07:00
arm-powerctl.c arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() 2019-12-20 14:03:00 +00:00
arm-powerctl.h target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() 2019-02-28 11:03:04 +00:00
cpu64.c hw/arm/virt: KVM: Enable PAuth when supported by the host 2022-01-20 11:47:52 +00:00
cpu_tcg.c target/arm: Implement arm_cpu_record_sigbus 2021-11-02 07:00:52 -04:00
cpu-param.h linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE 2021-02-16 13:06:16 +00:00
cpu-qom.h qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
cpu.c target/arm: make psci-conduit settable after realize 2022-02-08 10:56:27 +00:00
cpu.h hw/arm/virt: KVM: Enable PAuth when supported by the host 2022-01-20 11:47:52 +00:00
crypto_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
debug_helper.c target/arm: Suppress bp for exceptions with more priority 2021-12-15 10:35:26 +00:00
gdbstub64.c target/arm: Move gdbstub related code out of helper.c 2021-09-30 13:42:10 +01:00
gdbstub.c target/arm: Assert thumb pc is aligned 2021-12-15 10:35:26 +00:00
helper-a64.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
helper-a64.h target/arm: Merge mte_check1, mte_checkN 2021-04-30 11:16:49 +01:00
helper-mve.h target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
helper-sve.h target/arm: Implement vector float32 to bfloat16 conversion 2021-06-03 16:43:26 +01:00
helper.c target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_el 2022-02-08 10:56:27 +00:00
helper.h target/arm: Take an exception if PC is misaligned 2021-12-15 10:35:26 +00:00
hvf_arm.h hvf: arm: Implement -cpu host 2021-09-21 16:28:26 +01:00
idau.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
internals.h target/arm: Log CPU index in 'Taking exception' log 2022-01-28 14:29:47 +00:00
iwmmxt_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm64.c hw/arm/virt: KVM: Enable PAuth when supported by the host 2022-01-20 11:47:52 +00:00
kvm_arm.h hvf: arm: Implement -cpu host 2021-09-21 16:28:26 +01:00
kvm-consts.h target/arm: Remove no-longer-reachable 32-bit KVM code 2020-09-14 14:23:19 +01:00
kvm-stub.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
kvm.c memory: Name all the memory listeners 2021-09-30 15:30:24 +02:00
m_helper.c target/arm: Log CPU index in 'Taking exception' log 2022-01-28 14:29:47 +00:00
m-nocp.decode target/arm: Don't NOCP fault for FPCXT_NS accesses 2021-06-21 16:49:37 +01:00
machine.c target/arm: Assert thumb pc is aligned 2021-12-15 10:35:26 +00:00
meson.build arm: Add Hypervisor.framework build target 2021-09-21 16:28:26 +01:00
monitor.c target/arm: Add cpu properties to control pauth 2021-01-19 14:38:51 +00:00
mte_helper.c target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup 2021-11-02 07:00:52 -04:00
mve_helper.c target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
mve.decode target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
neon_helper.c target/arm: Split out saturating/rounding shifts from neon 2021-05-25 16:01:43 +01:00
neon-dp.decode target/arm: Implement vector float32 to bfloat16 conversion 2021-06-03 16:43:26 +01:00
neon-ls.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
neon-shared.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
op_addsub.h
op_helper.c target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
pauth_helper.c target/arm: Implement an IMPDEF pauth algorithm 2021-01-19 14:38:51 +00:00
psci.c arm: tcg: Adhere to SMCCC 1.3 section 5.2 2022-02-08 10:56:28 +00:00
sve_helper.c target/arm: Fixup comment re handle_cpu_signal 2021-11-02 07:00:52 -04:00
sve.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
syndrome.h target/arm: Take an exception if PC is misaligned 2021-12-15 10:35:26 +00:00
t16.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
t32.decode target/arm: Implement MVE VCTP 2021-08-25 10:48:50 +01:00
tlb_helper.c target/arm: Take an exception if PC is misaligned 2021-12-15 10:35:26 +00:00
trace-events docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate-a32.h exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate-a64.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate-a64.h target/arm: Implement SVE2 XAR 2021-05-25 16:01:44 +01:00
translate-m-nocp.c target/arm: Add TB flag for "MVE insns not predicated" 2021-09-21 16:28:27 +01:00
translate-mve.c target/arm: Optimize MVE 1op-immediate insns 2021-09-21 16:28:27 +01:00
translate-neon.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate-sve.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate-vfp.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
translate.h target/arm: Add TB flag for "MVE insns not predicated" 2021-09-21 16:28:27 +01:00
vec_helper.c target/arm: Implement MVE VMULL (polynomial) 2021-08-25 10:48:49 +01:00
vec_internal.h target/arm: Implement MVE VMULL (polynomial) 2021-08-25 10:48:49 +01:00
vfp_helper.c target/arm: Check NaN mode before silencing NaN 2021-07-02 11:48:36 +01:00
vfp-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
vfp.decode target/arm: Don't NOCP fault for FPCXT_NS accesses 2021-06-21 16:49:37 +01:00