qemu/tcg/riscv
Richard Henderson 3ea9be3340 tcg/riscv: Conditionalize tcg_out_exts_i32_i64
Since TCG_TYPE_I32 values are kept sign-extended in registers, via "w"
instructions, we don't need to extend if the register matches.
This is already relied upon by comparisons.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-23 08:46:45 +01:00
..
tcg-target-con-set.h tcg/riscv: Split out constraint sets to tcg-target-con-set.h 2021-02-02 12:12:43 -10:00
tcg-target-con-str.h tcg/riscv: Split out target constraints to tcg-target-con-str.h 2021-02-02 12:12:31 -10:00
tcg-target.c.inc tcg/riscv: Conditionalize tcg_out_exts_i32_i64 2023-04-23 08:46:45 +01:00
tcg-target.h tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128 2023-02-04 06:19:42 -10:00