3e80f6902c
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
|
|
* QEMU SiFive Test Finisher
|
|
*
|
|
* Copyright (c) 2018 SiFive, Inc.
|
|
*
|
|
* Test finisher memory mapped device used to exit simulation
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2 or later, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include "qemu/osdep.h"
|
|
#include "hw/sysbus.h"
|
|
#include "qapi/error.h"
|
|
#include "qemu/log.h"
|
|
#include "qemu/module.h"
|
|
#include "sysemu/runstate.h"
|
|
#include "hw/hw.h"
|
|
#include "hw/riscv/sifive_test.h"
|
|
|
|
static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void sifive_test_write(void *opaque, hwaddr addr,
|
|
uint64_t val64, unsigned int size)
|
|
{
|
|
if (addr == 0) {
|
|
int status = val64 & 0xffff;
|
|
int code = (val64 >> 16) & 0xffff;
|
|
switch (status) {
|
|
case FINISHER_FAIL:
|
|
exit(code);
|
|
case FINISHER_PASS:
|
|
exit(0);
|
|
case FINISHER_RESET:
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
|
return;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
|
|
__func__, (int)addr, val64);
|
|
}
|
|
|
|
static const MemoryRegionOps sifive_test_ops = {
|
|
.read = sifive_test_read,
|
|
.write = sifive_test_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4
|
|
}
|
|
};
|
|
|
|
static void sifive_test_init(Object *obj)
|
|
{
|
|
SiFiveTestState *s = SIFIVE_TEST(obj);
|
|
|
|
memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
|
|
TYPE_SIFIVE_TEST, 0x1000);
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
|
|
}
|
|
|
|
static const TypeInfo sifive_test_info = {
|
|
.name = TYPE_SIFIVE_TEST,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(SiFiveTestState),
|
|
.instance_init = sifive_test_init,
|
|
};
|
|
|
|
static void sifive_test_register_types(void)
|
|
{
|
|
type_register_static(&sifive_test_info);
|
|
}
|
|
|
|
type_init(sifive_test_register_types)
|
|
|
|
|
|
/*
|
|
* Create Test device.
|
|
*/
|
|
DeviceState *sifive_test_create(hwaddr addr)
|
|
{
|
|
DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
|
|
qdev_realize_and_unref(dev, NULL, &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
|
|
return dev;
|
|
}
|