Sia Jee Heng 3e6f1e61b4 hw/riscv/virt-acpi-build.c: Generate SPCR table ... Generate Serial Port Console Redirection Table (SPCR) for RISC-V virtual machine. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-03-08 15:40:08 +10:00
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boot.c	target/riscv: Move misa_mxl_max to class	2024-02-09 20:43:14 +10:00
Kconfig	target/riscv: SMBIOS support for RISC-V virt machine	2024-02-09 20:43:14 +10:00
meson.build	hw/riscv/virt: Enable basic ACPI infrastructure	2023-03-06 11:35:04 -08:00
microchip_pfsoc.c	hw/riscv: use qemu_configure_nic_device()	2024-02-02 16:23:47 +00:00
numa.c	hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()	2024-02-09 20:43:14 +10:00
opentitan.c	hw/riscv: opentitan: Fixup local variables shadowing	2023-09-29 10:07:20 +02:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv/shakti_c: Check CPU type in machine_run_board_init()	2024-01-05 16:20:15 +01:00
sifive_e.c	riscv: Fix SiFive E CLINT clock frequency	2023-11-22 13:57:19 +10:00
sifive_u.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00
spike.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00
virt-acpi-build.c	hw/riscv/virt-acpi-build.c: Generate SPCR table	2024-03-08 15:40:08 +10:00
virt.c	target/riscv: SMBIOS support for RISC-V virt machine	2024-02-09 20:43:14 +10:00