Richard Henderson 3e0e16ae1e target/microblaze: Fix width of MSR ... The machine status register is only 32-bits wide. Do not use a 64-bit type to represent it. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2020-09-01 07:41:38 -07:00
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alpha	meson: target	2020-08-21 06:30:35 -04:00
arm	target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd	2020-08-28 10:02:50 +01:00
avr	meson: target	2020-08-21 06:30:35 -04:00
cris	meson: target	2020-08-21 06:30:35 -04:00
hppa	meson: target	2020-08-21 06:30:35 -04:00
i386	hvf: Move HVFState typedef to hvf.h	2020-08-27 14:04:54 -04:00
lm32	meson: target	2020-08-21 06:30:35 -04:00
m68k	meson: target	2020-08-21 06:30:35 -04:00
microblaze	target/microblaze: Fix width of MSR	2020-09-01 07:41:38 -07:00
mips	meson: target	2020-08-21 06:30:35 -04:00
moxie	meson: target	2020-08-21 06:30:35 -04:00
nios2	meson: target	2020-08-21 06:30:35 -04:00
openrisc	meson: target	2020-08-21 06:30:35 -04:00
ppc	ppc patch queue 2020-08-18	2020-08-24 09:35:21 +01:00
riscv	softfloat: Implement the full set of comparisons for float16	2020-08-28 10:48:07 -07:00
rx	meson: target	2020-08-21 06:30:35 -04:00
s390x	target/s390x: fix meson.build issue	2020-08-21 11:55:13 -04:00
sh4	meson: target	2020-08-21 06:30:35 -04:00
sparc	meson: target	2020-08-21 06:30:35 -04:00
tilegx	meson: target	2020-08-21 06:30:35 -04:00
tricore	meson: target	2020-08-21 06:30:35 -04:00
unicore32	meson: target	2020-08-21 06:30:35 -04:00
xtensa	target/xtensa: import DSP3400 core	2020-08-21 12:56:45 -07:00
meson.build	meson: target	2020-08-21 06:30:35 -04:00