Frank Chang 3dd2168c33 target/riscv: Add Zc extension implied rule ... Zc extension has special implied rules that need to be handled separately. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-6-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-06-26 23:12:21 +10:00
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meson.build	target/riscv: introduce TCG AccelCPUClass	2023-10-12 11:55:21 +10:00
tcg-cpu.c	target/riscv: Add Zc extension implied rule	2024-06-26 23:12:21 +10:00
tcg-cpu.h	target/riscv: Implement dynamic establishment of custom decoder	2024-06-03 11:12:12 +10:00