b636db306e
Switch the cadence uart to multi-phase reset and add the reference clock input. The input clock frequency is added to the migration structure. The reference clock controls the baudrate generation. If it disabled, any input characters and events are ignored. If this clock remains unconnected, the uart behaves as before (it default to a 50MHz ref clock). Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200406135251.157596-8-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
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* Device model for Cadence UART
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*
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* Copyright (c) 2010 Xilinx Inc.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Written by Haibing Ma
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* M.Habib
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CADENCE_UART_H
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#define CADENCE_UART_H
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#include "qemu/timer.h"
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#define CADENCE_UART_RX_FIFO_SIZE 16
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#define CADENCE_UART_TX_FIFO_SIZE 16
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#define CADENCE_UART_R_MAX (0x48/4)
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#define TYPE_CADENCE_UART "cadence_uart"
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#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
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TYPE_CADENCE_UART)
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typedef struct {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t r[CADENCE_UART_R_MAX];
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uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
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uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
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uint32_t rx_wpos;
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uint32_t rx_count;
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uint32_t tx_count;
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uint64_t char_tx_time;
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CharBackend chr;
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qemu_irq irq;
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QEMUTimer *fifo_trigger_handle;
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Clock *refclk;
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} CadenceUARTState;
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static inline DeviceState *cadence_uart_create(hwaddr addr,
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qemu_irq irq,
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Chardev *chr)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, TYPE_CADENCE_UART);
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s = SYS_BUS_DEVICE(dev);
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qdev_prop_set_chr(dev, "chardev", chr);
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qdev_init_nofail(dev);
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sysbus_mmio_map(s, 0, addr);
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sysbus_connect_irq(s, 0, irq);
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return dev;
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}
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#endif
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