Richard Henderson 3cb506a399 target/arm: Reformat integer register dump ... With PC, there are 33 registers. Three per line lines up nicely without overflowing 80 columns. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2018-08-16 14:05:28 +01:00
..
alpha	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-01 15:15:27 -07:00
arm	target/arm: Reformat integer register dump	2018-08-16 14:05:28 +01:00
cris	tcg-next queue	2018-06-04 11:28:31 +01:00
hppa	tcg-next queue	2018-06-04 11:28:31 +01:00
i386	i386: implement MSR_SMI_COUNT for TCG	2018-07-30 14:00:11 +02:00
lm32	tcg-next queue	2018-06-04 11:28:31 +01:00
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-11 12:43:42 +02:00
microblaze	target-microblaze: Rework NOP/zero instruction handling	2018-06-15 09:05:00 +02:00
mips	target/mips: Fix gdbstub to read/write 64 bit FP registers	2018-06-27 20:13:50 +02:00
moxie	tcg-next queue	2018-06-04 11:28:31 +01:00
nios2	tcg-next queue	2018-06-04 11:28:31 +01:00
openrisc	target/openrisc: Fix writes to interrupt mask register	2018-07-03 22:40:33 +09:00
ppc	target/ppc: fix build on ppc64 host	2018-07-07 12:12:27 +10:00
riscv	RISC-V: Add trailing '\n' to qemu_log() calls	2018-06-08 13:15:33 +01:00
s390x	s390x/cpumodel: fix segmentation fault when baselining models	2018-07-18 14:20:02 +02:00
sh4	target/sh4: Fix translator.c assertion failure for gUSA	2018-07-09 10:34:04 -07:00
sparc	SPARC64: add icount support	2018-06-17 11:13:06 +01:00
tilegx	tcg-next queue	2018-06-04 11:28:31 +01:00
tricore	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-01 15:15:27 -07:00
unicore32	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-01 15:15:27 -07:00
xtensa	target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfn	2018-08-06 19:07:21 +01:00