3c1cf9fa86
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@311 c046a42c-6fe2-441c-8c8c-71466251a162
321 lines
8.5 KiB
C
321 lines
8.5 KiB
C
/*
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* i386 virtual CPU header
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#include <setjmp.h>
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK (1 << 23)
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#define DESC_B_SHIFT 22
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#define DESC_B_MASK (1 << DESC_B_SHIFT)
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#define DESC_AVL_MASK (1 << 20)
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#define DESC_P_MASK (1 << 15)
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#define DESC_DPL_SHIFT 13
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#define DESC_S_MASK (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_A_MASK (1 << 8)
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#define DESC_CS_MASK (1 << 11)
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#define DESC_C_MASK (1 << 10)
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#define DESC_R_MASK (1 << 9)
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#define DESC_E_MASK (1 << 10)
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#define DESC_W_MASK (1 << 9)
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/* eflags masks */
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#define CC_C 0x0001
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#define CC_P 0x0004
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#define CC_A 0x0010
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#define CC_Z 0x0040
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#define CC_S 0x0080
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#define CC_O 0x0800
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#define TF_MASK 0x00000100
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#define IF_MASK 0x00000200
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#define DF_MASK 0x00000400
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#define IOPL_MASK 0x00003000
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#define NT_MASK 0x00004000
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#define RF_MASK 0x00010000
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#define VM_MASK 0x00020000
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#define AC_MASK 0x00040000
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#define VIF_MASK 0x00080000
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#define VIP_MASK 0x00100000
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#define ID_MASK 0x00200000
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#define CR0_PE_MASK (1 << 0)
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#define CR0_TS_MASK (1 << 3)
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#define CR0_WP_MASK (1 << 16)
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#define CR0_AM_MASK (1 << 18)
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#define CR0_PG_MASK (1 << 31)
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#define CR4_VME_MASK (1 << 0)
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#define CR4_PVI_MASK (1 << 1)
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#define CR4_TSD_MASK (1 << 2)
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#define CR4_DE_MASK (1 << 3)
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#define CR4_PSE_MASK (1 << 4)
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#define PG_PRESENT_BIT 0
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#define PG_RW_BIT 1
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#define PG_USER_BIT 2
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#define PG_PWT_BIT 3
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#define PG_PCD_BIT 4
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#define PG_ACCESSED_BIT 5
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#define PG_DIRTY_BIT 6
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#define PG_PSE_BIT 7
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#define PG_GLOBAL_BIT 8
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#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK (1 << PG_RW_BIT)
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#define PG_USER_MASK (1 << PG_USER_BIT)
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#define PG_PWT_MASK (1 << PG_PWT_BIT)
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#define PG_PCD_MASK (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
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#define PG_ERROR_W_BIT 1
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#define PG_ERROR_P_MASK 0x01
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#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
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#define PG_ERROR_U_MASK 0x04
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#define PG_ERROR_RSVD_MASK 0x08
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#define MSR_IA32_APICBASE 0x1b
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#define MSR_IA32_APICBASE_BSP (1<<8)
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_SYSENTER_CS 0x174
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#define MSR_IA32_SYSENTER_ESP 0x175
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#define MSR_IA32_SYSENTER_EIP 0x176
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#define EXCP00_DIVZ 0
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#define EXCP01_SSTP 1
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#define EXCP02_NMI 2
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#define EXCP03_INT3 3
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#define EXCP04_INTO 4
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#define EXCP05_BOUND 5
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#define EXCP06_ILLOP 6
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#define EXCP07_PREX 7
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#define EXCP08_DBLE 8
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#define EXCP09_XERR 9
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#define EXCP0A_TSS 10
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#define EXCP0B_NOSEG 11
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#define EXCP0C_STACK 12
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#define EXCP0D_GPF 13
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#define EXCP0E_PAGE 14
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#define EXCP10_COPR 16
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#define EXCP11_ALGN 17
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#define EXCP12_MCHK 18
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#define EXCP_INTERRUPT 256 /* async interruption */
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#define EXCP_HLT 257 /* hlt instruction reached */
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enum {
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CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
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CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_ADDW,
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CC_OP_ADDL,
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CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_ADCW,
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CC_OP_ADCL,
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CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_SUBW,
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CC_OP_SUBL,
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CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_SBBW,
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CC_OP_SBBL,
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CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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CC_OP_LOGICW,
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CC_OP_LOGICL,
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CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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CC_OP_INCW,
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CC_OP_INCL,
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CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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CC_OP_DECW,
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CC_OP_DECL,
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CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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CC_OP_SHLW,
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CC_OP_SHLL,
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CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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CC_OP_SARW,
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CC_OP_SARL,
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CC_OP_NB,
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};
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#ifdef __i386__
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#define USE_X86LDOUBLE
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#endif
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#ifdef USE_X86LDOUBLE
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typedef long double CPU86_LDouble;
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#else
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typedef double CPU86_LDouble;
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#endif
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typedef struct SegmentCache {
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uint32_t selector;
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uint8_t *base;
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uint32_t limit;
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uint32_t flags;
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} SegmentCache;
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typedef struct CPUX86State {
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/* standard registers */
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uint32_t regs[8];
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uint32_t eip;
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uint32_t eflags; /* eflags register. During CPU emulation, CC
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flags and DF are set to zero because they are
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stored elsewhere */
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/* emulator internal eflags handling */
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uint32_t cc_src;
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uint32_t cc_dst;
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uint32_t cc_op;
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int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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/* FPU state */
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unsigned int fpstt; /* top of stack index */
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unsigned int fpus;
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unsigned int fpuc;
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uint8_t fptags[8]; /* 0 = valid, 1 = empty */
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CPU86_LDouble fpregs[8];
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/* emulator internal variables */
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CPU86_LDouble ft0;
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union {
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float f;
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double d;
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int i32;
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int64_t i64;
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} fp_convert;
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/* segments */
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SegmentCache segs[6]; /* selector values */
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SegmentCache ldt;
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SegmentCache tr;
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SegmentCache gdt; /* only base and limit are used */
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SegmentCache idt; /* only base and limit are used */
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/* sysenter registers */
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uint32_t sysenter_cs;
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uint32_t sysenter_esp;
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uint32_t sysenter_eip;
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/* exception/interrupt handling */
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jmp_buf jmp_env;
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int exception_index;
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int error_code;
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int exception_is_int;
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int exception_next_eip;
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struct TranslationBlock *current_tb; /* currently executing TB */
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uint32_t cr[5]; /* NOTE: cr1 is unused */
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uint32_t dr[8]; /* debug registers */
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int interrupt_request;
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int user_mode_only; /* user mode only simulation */
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/* user data */
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void *opaque;
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} CPUX86State;
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#ifndef IN_OP_I386
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void cpu_x86_outb(CPUX86State *env, int addr, int val);
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void cpu_x86_outw(CPUX86State *env, int addr, int val);
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void cpu_x86_outl(CPUX86State *env, int addr, int val);
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int cpu_x86_inb(CPUX86State *env, int addr);
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int cpu_x86_inw(CPUX86State *env, int addr);
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int cpu_x86_inl(CPUX86State *env, int addr);
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#endif
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CPUX86State *cpu_x86_init(void);
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int cpu_x86_exec(CPUX86State *s);
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void cpu_x86_close(CPUX86State *s);
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int cpu_x86_get_pic_interrupt(CPUX86State *s);
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/* needed to load some predefinied segment registers */
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void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
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/* simulate fsave/frstor */
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void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
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void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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struct siginfo;
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc);
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/* MMU defines */
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void cpu_x86_init_mmu(CPUX86State *env);
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extern int phys_ram_size;
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extern int phys_ram_fd;
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extern uint8_t *phys_ram_base;
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/* used to debug */
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#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
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#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
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void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
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#define TARGET_PAGE_BITS 12
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#include "cpu-all.h"
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#endif /* CPU_I386_H */
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