3b77c289ae
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
122 lines
5.5 KiB
Plaintext
122 lines
5.5 KiB
Plaintext
#
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# RISC-V translation routines for the RVXI Base Integer Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# Fields:
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%rs2 20:5
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%rs1 15:5
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%rd 7:5
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%sh10 20:10
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%csr 20:12
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# immediates:
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%imm_i 20:s12
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%imm_s 25:s7 7:5
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%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
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%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
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%imm_u 12:s20 !function=ex_shift_12
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# Argument sets:
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&b imm rs2 rs1
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&shift shamt rs1 rd
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&atomic aq rl rs2 rs1 rd
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# Formats 32:
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@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
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@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
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@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
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@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
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@u .................... ..... ....... imm=%imm_u %rd
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@j .................... ..... ....... imm=%imm_j %rd
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@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
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@csr ............ ..... ... ..... ....... %csr %rs1 %rd
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@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
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@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
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# *** RV32I Base Instruction Set ***
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lui .................... ..... 0110111 @u
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auipc .................... ..... 0010111 @u
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jal .................... ..... 1101111 @j
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jalr ............ ..... 000 ..... 1100111 @i
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beq ....... ..... ..... 000 ..... 1100011 @b
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bne ....... ..... ..... 001 ..... 1100011 @b
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blt ....... ..... ..... 100 ..... 1100011 @b
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bge ....... ..... ..... 101 ..... 1100011 @b
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bltu ....... ..... ..... 110 ..... 1100011 @b
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bgeu ....... ..... ..... 111 ..... 1100011 @b
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lb ............ ..... 000 ..... 0000011 @i
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lh ............ ..... 001 ..... 0000011 @i
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lw ............ ..... 010 ..... 0000011 @i
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lbu ............ ..... 100 ..... 0000011 @i
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lhu ............ ..... 101 ..... 0000011 @i
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sb ....... ..... ..... 000 ..... 0100011 @s
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sh ....... ..... ..... 001 ..... 0100011 @s
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sw ....... ..... ..... 010 ..... 0100011 @s
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addi ............ ..... 000 ..... 0010011 @i
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slti ............ ..... 010 ..... 0010011 @i
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sltiu ............ ..... 011 ..... 0010011 @i
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xori ............ ..... 100 ..... 0010011 @i
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ori ............ ..... 110 ..... 0010011 @i
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andi ............ ..... 111 ..... 0010011 @i
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slli 00.... ...... ..... 001 ..... 0010011 @sh
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srli 00.... ...... ..... 101 ..... 0010011 @sh
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srai 01.... ...... ..... 101 ..... 0010011 @sh
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add 0000000 ..... ..... 000 ..... 0110011 @r
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sub 0100000 ..... ..... 000 ..... 0110011 @r
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sll 0000000 ..... ..... 001 ..... 0110011 @r
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slt 0000000 ..... ..... 010 ..... 0110011 @r
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sltu 0000000 ..... ..... 011 ..... 0110011 @r
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xor 0000000 ..... ..... 100 ..... 0110011 @r
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srl 0000000 ..... ..... 101 ..... 0110011 @r
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sra 0100000 ..... ..... 101 ..... 0110011 @r
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or 0000000 ..... ..... 110 ..... 0110011 @r
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and 0000000 ..... ..... 111 ..... 0110011 @r
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fence ---- pred:4 succ:4 ----- 000 ----- 0001111
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fence_i ---- ---- ---- ----- 001 ----- 0001111
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csrrw ............ ..... 001 ..... 1110011 @csr
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csrrs ............ ..... 010 ..... 1110011 @csr
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csrrc ............ ..... 011 ..... 1110011 @csr
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csrrwi ............ ..... 101 ..... 1110011 @csr
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csrrsi ............ ..... 110 ..... 1110011 @csr
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csrrci ............ ..... 111 ..... 1110011 @csr
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# *** RV32M Standard Extension ***
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mul 0000001 ..... ..... 000 ..... 0110011 @r
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mulh 0000001 ..... ..... 001 ..... 0110011 @r
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mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
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mulhu 0000001 ..... ..... 011 ..... 0110011 @r
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div 0000001 ..... ..... 100 ..... 0110011 @r
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divu 0000001 ..... ..... 101 ..... 0110011 @r
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rem 0000001 ..... ..... 110 ..... 0110011 @r
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remu 0000001 ..... ..... 111 ..... 0110011 @r
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# *** RV32A Standard Extension ***
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lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
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sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
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amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
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amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
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amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
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amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
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amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
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amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
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