eb51d102bb
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@169 c046a42c-6fe2-441c-8c8c-71466251a162
646 lines
15 KiB
C
646 lines
15 KiB
C
/*
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* i386 virtual CPU header
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#include <setjmp.h>
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* eflags masks */
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#define CC_C 0x0001
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#define CC_P 0x0004
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#define CC_A 0x0010
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#define CC_Z 0x0040
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#define CC_S 0x0080
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#define CC_O 0x0800
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#define TF_MASK 0x00000100
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#define IF_MASK 0x00000200
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#define DF_MASK 0x00000400
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#define IOPL_MASK 0x00003000
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#define NT_MASK 0x00004000
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#define RF_MASK 0x00010000
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#define VM_MASK 0x00020000
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#define AC_MASK 0x00040000
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#define VIF_MASK 0x00080000
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#define VIP_MASK 0x00100000
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#define ID_MASK 0x00200000
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#define EXCP00_DIVZ 0
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#define EXCP01_SSTP 1
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#define EXCP02_NMI 2
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#define EXCP03_INT3 3
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#define EXCP04_INTO 4
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#define EXCP05_BOUND 5
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#define EXCP06_ILLOP 6
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#define EXCP07_PREX 7
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#define EXCP08_DBLE 8
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#define EXCP09_XERR 9
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#define EXCP0A_TSS 10
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#define EXCP0B_NOSEG 11
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#define EXCP0C_STACK 12
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#define EXCP0D_GPF 13
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#define EXCP0E_PAGE 14
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#define EXCP10_COPR 16
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#define EXCP11_ALGN 17
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#define EXCP12_MCHK 18
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#define EXCP_INTERRUPT 256 /* async interruption */
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enum {
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CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
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CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_ADDW,
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CC_OP_ADDL,
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CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_ADCW,
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CC_OP_ADCL,
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CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_SUBW,
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CC_OP_SUBL,
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CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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CC_OP_SBBW,
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CC_OP_SBBL,
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CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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CC_OP_LOGICW,
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CC_OP_LOGICL,
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CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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CC_OP_INCW,
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CC_OP_INCL,
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CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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CC_OP_DECW,
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CC_OP_DECL,
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CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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CC_OP_SHLW,
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CC_OP_SHLL,
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CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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CC_OP_SARW,
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CC_OP_SARL,
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CC_OP_NB,
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};
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#ifdef __i386__
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#define USE_X86LDOUBLE
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#endif
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#ifdef USE_X86LDOUBLE
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typedef long double CPU86_LDouble;
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#else
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typedef double CPU86_LDouble;
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#endif
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typedef struct SegmentCache {
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uint8_t *base;
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unsigned long limit;
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uint8_t seg_32bit;
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} SegmentCache;
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typedef struct SegmentDescriptorTable {
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uint8_t *base;
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unsigned long limit;
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/* this is the returned base when reading the register, just to
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avoid that the emulated program modifies it */
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unsigned long emu_base;
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} SegmentDescriptorTable;
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typedef struct CPUX86State {
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/* standard registers */
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uint32_t regs[8];
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uint32_t eip;
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uint32_t eflags; /* eflags register. During CPU emulation, CC
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flags and DF are set to zero because they are
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stored elsewhere */
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/* emulator internal eflags handling */
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uint32_t cc_src;
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uint32_t cc_dst;
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uint32_t cc_op;
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int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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/* FPU state */
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unsigned int fpstt; /* top of stack index */
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unsigned int fpus;
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unsigned int fpuc;
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uint8_t fptags[8]; /* 0 = valid, 1 = empty */
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CPU86_LDouble fpregs[8];
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/* emulator internal variables */
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CPU86_LDouble ft0;
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union {
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float f;
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double d;
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int i32;
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int64_t i64;
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} fp_convert;
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/* segments */
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uint32_t segs[6]; /* selector values */
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SegmentCache seg_cache[6]; /* info taken from LDT/GDT */
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SegmentDescriptorTable gdt;
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SegmentDescriptorTable ldt;
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SegmentDescriptorTable idt;
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/* exception/interrupt handling */
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jmp_buf jmp_env;
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int exception_index;
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int error_code;
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uint32_t cr2;
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int interrupt_request;
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/* user data */
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void *opaque;
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} CPUX86State;
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/* all CPU memory access use these macros */
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static inline int ldub(void *ptr)
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{
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return *(uint8_t *)ptr;
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}
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static inline int ldsb(void *ptr)
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{
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return *(int8_t *)ptr;
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}
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static inline void stb(void *ptr, int v)
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{
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*(uint8_t *)ptr = v;
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}
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#ifdef WORDS_BIGENDIAN
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/* conservative code for little endian unaligned accesses */
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static inline int lduw(void *ptr)
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{
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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return val;
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#else
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uint8_t *p = ptr;
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return p[0] | (p[1] << 8);
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#endif
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}
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static inline int ldsw(void *ptr)
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{
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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return (int16_t)val;
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#else
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uint8_t *p = ptr;
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return (int16_t)(p[0] | (p[1] << 8));
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#endif
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}
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static inline int ldl(void *ptr)
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{
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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return val;
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#else
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uint8_t *p = ptr;
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return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
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#endif
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}
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static inline uint64_t ldq(void *ptr)
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{
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uint8_t *p = ptr;
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uint32_t v1, v2;
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v1 = ldl(p);
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v2 = ldl(p + 4);
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return v1 | ((uint64_t)v2 << 32);
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}
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static inline void stw(void *ptr, int v)
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{
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#ifdef __powerpc__
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__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
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#else
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uint8_t *p = ptr;
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p[0] = v;
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p[1] = v >> 8;
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#endif
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}
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static inline void stl(void *ptr, int v)
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{
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#ifdef __powerpc__
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__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
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#else
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uint8_t *p = ptr;
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p[0] = v;
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p[1] = v >> 8;
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p[2] = v >> 16;
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p[3] = v >> 24;
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#endif
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}
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static inline void stq(void *ptr, uint64_t v)
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{
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uint8_t *p = ptr;
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stl(p, (uint32_t)v);
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stl(p + 4, v >> 32);
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}
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/* float access */
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static inline float ldfl(void *ptr)
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{
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union {
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float f;
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uint32_t i;
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} u;
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u.i = ldl(ptr);
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return u.f;
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}
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static inline double ldfq(void *ptr)
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{
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union {
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double d;
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uint64_t i;
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} u;
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u.i = ldq(ptr);
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return u.d;
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}
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static inline void stfl(void *ptr, float v)
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{
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union {
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float f;
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uint32_t i;
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} u;
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u.f = v;
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stl(ptr, u.i);
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}
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static inline void stfq(void *ptr, double v)
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{
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union {
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double d;
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uint64_t i;
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} u;
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u.d = v;
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stq(ptr, u.i);
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}
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#else
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static inline int lduw(void *ptr)
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{
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return *(uint16_t *)ptr;
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}
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static inline int ldsw(void *ptr)
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{
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return *(int16_t *)ptr;
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}
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static inline int ldl(void *ptr)
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{
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return *(uint32_t *)ptr;
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}
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static inline uint64_t ldq(void *ptr)
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{
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return *(uint64_t *)ptr;
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}
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static inline void stw(void *ptr, int v)
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{
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*(uint16_t *)ptr = v;
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}
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static inline void stl(void *ptr, int v)
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{
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*(uint32_t *)ptr = v;
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}
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static inline void stq(void *ptr, uint64_t v)
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{
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*(uint64_t *)ptr = v;
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}
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/* float access */
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static inline float ldfl(void *ptr)
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{
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return *(float *)ptr;
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}
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static inline double ldfq(void *ptr)
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{
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return *(double *)ptr;
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}
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static inline void stfl(void *ptr, float v)
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{
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*(float *)ptr = v;
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}
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static inline void stfq(void *ptr, double v)
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{
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*(double *)ptr = v;
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}
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#endif
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#ifndef IN_OP_I386
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void cpu_x86_outb(CPUX86State *env, int addr, int val);
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void cpu_x86_outw(CPUX86State *env, int addr, int val);
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void cpu_x86_outl(CPUX86State *env, int addr, int val);
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int cpu_x86_inb(CPUX86State *env, int addr);
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int cpu_x86_inw(CPUX86State *env, int addr);
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int cpu_x86_inl(CPUX86State *env, int addr);
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#endif
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CPUX86State *cpu_x86_init(void);
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int cpu_x86_exec(CPUX86State *s);
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void cpu_x86_interrupt(CPUX86State *s);
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void cpu_x86_close(CPUX86State *s);
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/* needed to load some predefinied segment registers */
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void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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struct siginfo;
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc);
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/* used to debug */
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#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
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#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
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void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
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/* page related stuff */
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#define TARGET_PAGE_BITS 12
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#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
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#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
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#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
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extern unsigned long real_host_page_size;
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extern unsigned long host_page_bits;
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extern unsigned long host_page_size;
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extern unsigned long host_page_mask;
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#define HOST_PAGE_ALIGN(addr) (((addr) + host_page_size - 1) & host_page_mask)
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/* same as PROT_xxx */
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#define PAGE_READ 0x0001
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#define PAGE_WRITE 0x0002
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#define PAGE_EXEC 0x0004
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#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
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#define PAGE_VALID 0x0008
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/* original state of the write flag (used when tracking self-modifying
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code */
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#define PAGE_WRITE_ORG 0x0010
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void page_dump(FILE *f);
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int page_get_flags(unsigned long address);
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void page_set_flags(unsigned long start, unsigned long end, int flags);
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void page_unprotect_range(uint8_t *data, unsigned long data_size);
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/***************************************************/
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/* internal functions */
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#define GEN_FLAG_CODE32_SHIFT 0
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#define GEN_FLAG_ADDSEG_SHIFT 1
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#define GEN_FLAG_SS32_SHIFT 2
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#define GEN_FLAG_VM_SHIFT 3
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#define GEN_FLAG_ST_SHIFT 4
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#define GEN_FLAG_CPL_SHIFT 7
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#define GEN_FLAG_IOPL_SHIFT 9
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#define GEN_FLAG_TF_SHIFT 11
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int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size,
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int *gen_code_size_ptr,
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uint8_t *pc_start, uint8_t *cs_base, int flags,
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int *code_size_ptr);
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void cpu_x86_tblocks_init(void);
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void page_init(void);
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int page_unprotect(unsigned long address);
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#define CODE_GEN_MAX_SIZE 65536
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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#define CODE_GEN_HASH_BITS 15
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#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
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/* maximum total translate dcode allocated */
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#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
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//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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typedef struct TranslationBlock {
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unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
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unsigned long cs_base; /* CS base for this block */
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unsigned int flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint8_t *tc_ptr; /* pointer to the translated code */
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struct TranslationBlock *hash_next; /* next matching block */
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struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */
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} TranslationBlock;
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static inline unsigned int tb_hash_func(unsigned long pc)
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{
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return pc & (CODE_GEN_HASH_SIZE - 1);
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}
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void tb_flush(void);
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TranslationBlock *tb_alloc(unsigned long pc,
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unsigned long size);
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extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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extern uint8_t *code_gen_ptr;
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/* find a translation block in the translation cache. If not found,
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return NULL and the pointer to the last element of the list in pptb */
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static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
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unsigned long pc,
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unsigned long cs_base,
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unsigned int flags)
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{
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TranslationBlock **ptb, *tb;
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unsigned int h;
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h = tb_hash_func(pc);
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ptb = &tb_hash[h];
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for(;;) {
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tb = *ptb;
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if (!tb)
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break;
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if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
|
|
return tb;
|
|
ptb = &tb->hash_next;
|
|
}
|
|
*pptb = ptb;
|
|
return NULL;
|
|
}
|
|
|
|
#ifndef offsetof
|
|
#define offsetof(type, field) ((size_t) &((type *)0)->field)
|
|
#endif
|
|
|
|
#ifdef __powerpc__
|
|
static inline int testandset (int *p)
|
|
{
|
|
int ret;
|
|
__asm__ __volatile__ (
|
|
"0: lwarx %0,0,%1 ;"
|
|
" xor. %0,%3,%0;"
|
|
" bne 1f;"
|
|
" stwcx. %2,0,%1;"
|
|
" bne- 0b;"
|
|
"1: "
|
|
: "=&r" (ret)
|
|
: "r" (p), "r" (1), "r" (0)
|
|
: "cr0", "memory");
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef __i386__
|
|
static inline int testandset (int *p)
|
|
{
|
|
char ret;
|
|
long int readval;
|
|
|
|
__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
|
|
: "=q" (ret), "=m" (*p), "=a" (readval)
|
|
: "r" (1), "m" (*p), "a" (0)
|
|
: "memory");
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef __s390__
|
|
static inline int testandset (int *p)
|
|
{
|
|
int ret;
|
|
|
|
__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
|
" jl 0b"
|
|
: "=&d" (ret)
|
|
: "r" (1), "a" (p), "0" (*p)
|
|
: "cc", "memory" );
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef __alpha__
|
|
int testandset (int *p)
|
|
{
|
|
int ret;
|
|
unsigned long one;
|
|
|
|
__asm__ __volatile__ ("0: mov 1,%2\n"
|
|
" ldl_l %0,%1\n"
|
|
" stl_c %2,%1\n"
|
|
" beq %2,1f\n"
|
|
".subsection 2\n"
|
|
"1: br 0b\n"
|
|
".previous"
|
|
: "=r" (ret), "=m" (*p), "=r" (one)
|
|
: "m" (*p));
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef __sparc__
|
|
static inline int testandset (int *p)
|
|
{
|
|
int ret;
|
|
|
|
__asm__ __volatile__("ldstub [%1], %0"
|
|
: "=r" (ret)
|
|
: "r" (p)
|
|
: "memory");
|
|
|
|
return (ret ? 1 : 0);
|
|
}
|
|
#endif
|
|
|
|
typedef int spinlock_t;
|
|
|
|
#define SPIN_LOCK_UNLOCKED 0
|
|
|
|
static inline void spin_lock(spinlock_t *lock)
|
|
{
|
|
while (testandset(lock));
|
|
}
|
|
|
|
static inline void spin_unlock(spinlock_t *lock)
|
|
{
|
|
*lock = 0;
|
|
}
|
|
|
|
static inline int spin_trylock(spinlock_t *lock)
|
|
{
|
|
return !testandset(lock);
|
|
}
|
|
|
|
extern spinlock_t tb_lock;
|
|
|
|
#endif /* CPU_I386_H */
|