88446cfe06
For USART, GPIO and SYSCFG devices, check that clock frequency before and after enabling the peripheral clock in RCC is correct. Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241003081105.40836-4-ines.varhol@telecom-paris.fr [PMM: Added missing qtest_quit() call] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/*
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* QTest testcase header for STM32L4X5 :
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* used for consolidating common objects in stm32l4x5_*-test.c
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*
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* Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "libqtest.h"
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/* copied from clock.h */
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#define CLOCK_PERIOD_1SEC (1000000000llu << 32)
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#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) != 0) ? CLOCK_PERIOD_1SEC / (hz) : 0u)
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/*
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* MSI (4 MHz) is used as system clock source after startup
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* from Reset.
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* AHB, APB1 and APB2 prescalers are set to 1 at reset.
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*/
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#define SYSCLK_PERIOD CLOCK_PERIOD_FROM_HZ(4000000)
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#define RCC_AHB2ENR 0x4002104C
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#define RCC_APB1ENR1 0x40021058
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#define RCC_APB1ENR2 0x4002105C
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#define RCC_APB2ENR 0x40021060
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static inline uint64_t get_clock_period(QTestState *qts, const char *path)
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{
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uint64_t clock_period = 0;
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QDict *r;
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r = qtest_qmp(qts, "{ 'execute': 'qom-get', 'arguments':"
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" { 'path': %s, 'property': 'qtest-clock-period'} }", path);
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g_assert_false(qdict_haskey(r, "error"));
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clock_period = qdict_get_int(r, "return");
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qobject_unref(r);
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return clock_period;
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}
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