qemu/target/hexagon/imported
Taylor Simpson a5a8d98c85 Hexagon (target/hexagon) fix l2fetch instructions
Y4_l2fetch == l2fetch(Rs32, Rt32)
Y5_l2fetch == l2fetch(Rs32, Rtt32)

The semantics for these instructions are present, but the encodings
are missing.

Note that these are treated as nops in qemu, so we add overrides.

Test case added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1622589584-22571-3-git-send-email-tsimpson@quicinc.com>
2021-06-29 11:32:50 -05:00
..
allidefs.def
alu.idef Hexagon (target/hexagon) add A4_addp_c/A4_subp_c 2021-05-01 08:31:43 -07:00
branch.idef
compare.idef Hexagon (target/hexagon) cleanup ternary operators in semantics 2021-05-01 08:31:43 -07:00
encode_pp.def Hexagon (target/hexagon) fix l2fetch instructions 2021-06-29 11:32:50 -05:00
encode_subinsn.def
encode.def
float.idef Hexagon (target/hexagon) add F2_sfinvsqrta 2021-05-01 08:31:43 -07:00
iclass.def
ldst.idef Hexagon (target/hexagon) load into shifted register instructions 2021-05-01 16:06:11 -07:00
macros.def Hexagon (target/hexagon) CABAC decode bin 2021-05-01 16:06:11 -07:00
mpy.idef
shift.idef Hexagon (target/hexagon) CABAC decode bin 2021-05-01 16:06:11 -07:00
subinsns.idef
system.idef