qemu/include at 38e65936a8df1c9e7f5d19eae38a42133fab844b - qemu

History

Stefan Hajnoczi 0b710ae5c5 target-arm queue:

* hw/sd: Fix sun4i allwinner-sdhost for U-Boot
  * hw/intc: add implementation of GICD_IIDR to Arm GIC
  * tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
  * target/arm: Limit LPA2 effective output address when TCR.DS == 0
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Merge tag 'pull-target-arm-20221121' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/sd: Fix sun4i allwinner-sdhost for U-Boot
 * hw/intc: add implementation of GICD_IIDR to Arm GIC
 * tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
 * target/arm: Limit LPA2 effective output address when TCR.DS == 0

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# gpg: Signature made Mon 21 Nov 2022 07:59:23 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20221121' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Limit LPA2 effective output address when TCR.DS == 0
  tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
  hw/intc: add implementation of GICD_IIDR to Arm GIC
  hw/intc: clean-up access to GIC multi-byte registers
  hw/sd: Fix sun4i allwinner-sdhost for U-Boot

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

2022-11-21 09:26:34 -05:00

authz

…

block

block: Make bdrv_child_get_parent_aio_context I/O

2022-11-10 14:58:34 +01:00

chardev

…

crypto

crypto: Support export akcipher to pkcs8

2022-11-02 06:56:32 -04:00

disas