qemu/fpu
Peter Maydell 38970efafd softfloat: Fix exception flag handling for float32_to_float16()
Our float32 to float16 conversion routine was generating the correct
numerical answers, but not always setting the right set of exception
flags. Fix this, mostly by rearranging the code to more closely
resemble RoundAndPackFloat*, and in particular:
 * non-IEEE halfprec always raises Invalid for input NaNs
 * we need to check for the overflow case before underflow
 * we weren't getting the tininess-detected-after-rounding
   case correct (somewhat academic since only ARM uses halfprec
   and it is always tininess-detected-before-rounding)
 * non-IEEE halfprec overflow raises only Invalid, not
   Invalid + Inexact
 * we weren't setting Inexact when we should

Also add some clarifying comments about what the code is doing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08 19:07:22 +00:00
..
softfloat-macros.h softfloat: Fix shift128Right for shift counts 64..127 2013-06-10 11:36:12 -05:00
softfloat-specialize.h softfloat: implement fused multiply-add NaN propagation for MIPS 2012-10-31 22:20:45 +01:00
softfloat.c softfloat: Fix exception flag handling for float32_to_float16() 2014-01-08 19:07:22 +00:00