Jonathan Cameron 388d6b574e hw/cxl: Use switch statements for read and write of cachemem registers ... Establishing that only register accesses of size 4 and 8 can occur using these functions requires looking at their callers. Make it easier to see that by using switch statements. Assertions are used to enforce that the register storage is of the matching size, allowing fixed values to be used for divisors of the array indices. Suggested-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Message-Id: <20231023140210.3089-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2023-11-07 03:39:11 -05:00
..
cxl-cdat.c	hw/cxl: cdat: Fix failure to free buffer in erorr paths	2023-05-19 01:36:09 -04:00
cxl-component-utils.c	hw/cxl: Use switch statements for read and write of cachemem registers	2023-11-07 03:39:11 -05:00
cxl-device-utils.c	hw/cxl: Use a switch to explicitly check size in caps_reg_read()	2023-11-07 03:39:11 -05:00
cxl-events.c	hw/other: spelling fixes	2023-09-21 11:31:16 +03:00
cxl-host-stubs.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
cxl-host.c	hw/cxl: Support 4 HDM decoders at all levels of topology	2023-10-04 18:15:06 -04:00
cxl-mailbox-utils.c	hw/other: spelling fixes	2023-09-21 11:31:16 +03:00
Kconfig
meson.build	hw/cxl/events: Wire up get/clear event mailbox commands	2023-06-22 18:55:14 -04:00