Alistair Francis 3847289054 riscv: Don't use stage-2 PTE lookup protection flags ...

When doing the fist of a two stage lookup (Hypervisor extensions) don't
set the current protection flags from the second stage lookup of the
base address PTE.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Anup Patel <anup@brainfault.org>
Message-id: 931db85d6890ed4bc2b527fd1011197cd28299aa.1585262586.git.alistair.francis@wdc.com
Message-Id: <931db85d6890ed4bc2b527fd1011197cd28299aa.1585262586.git.alistair.francis@wdc.com>

2020-04-29 13:16:36 -07:00

..

insn_trans

target/riscv: Remove the hret instruction

2020-02-27 13:45:45 -08:00

cpu_bits.h

target/riscv: Add the MSTATUS_MPV_ISSET helper macro

2020-02-27 13:46:33 -08:00

cpu_helper.c

riscv: Don't use stage-2 PTE lookup protection flags

2020-04-29 13:16:36 -07:00

cpu_user.h

…

cpu-param.h

…

cpu.c

cpu: Use DeviceClass reset instead of a special CPUClass reset

2020-03-17 19:48:10 -04:00

cpu.h

x86 and machine queue for 5.0 soft freeze

2020-03-19 14:22:46 +00:00

csr.c

target/riscv: Emulate TIME CSRs for privileged mode

2020-02-27 13:46:36 -08:00

fpu_helper.c

…

gdbstub.c

gdbstub: extend GByteArray to read register helpers

2020-03-17 17:38:38 +00:00

helper.h

…

insn16-32.decode

…

insn16-64.decode

…

insn16.decode

…

insn32-64.decode

…

insn32.decode

target/riscv: Remove the hret instruction

2020-02-27 13:45:45 -08:00

instmap.h

target/riscv: progressively load the instruction during decode

2020-02-25 20:20:23 +00:00

Makefile.objs

…

monitor.c

…

op_helper.c

target/riscv: Correctly implement TSR trap

2020-03-16 17:03:13 -07:00

pmp.c

…

pmp.h

…

trace-events

…

translate.c

target/riscv: Add the MSTATUS_MPV_ISSET helper macro

2020-02-27 13:46:33 -08:00