383beda9cf
Isolate the computation of an index from an address into a helper before we change that function. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [ cota: convert tlb_vaddr_to_host; use atomic_read on addr_write ] Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20181009175129.17888-2-cota@braap.org>
447 lines
15 KiB
C
447 lines
15 KiB
C
/*
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* Software MMU support
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*
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* Generate helpers used by TCG for qemu_ld/st ops and code load
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* functions.
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*
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* Included from target op helpers and exec.c.
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if DATA_SIZE == 8
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#define SUFFIX q
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#define LSUFFIX q
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#define SDATA_TYPE int64_t
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#define DATA_TYPE uint64_t
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#elif DATA_SIZE == 4
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#define SUFFIX l
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#define LSUFFIX l
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#define SDATA_TYPE int32_t
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#define DATA_TYPE uint32_t
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#elif DATA_SIZE == 2
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#define SUFFIX w
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#define LSUFFIX uw
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#define SDATA_TYPE int16_t
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#define DATA_TYPE uint16_t
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#elif DATA_SIZE == 1
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#define SUFFIX b
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#define LSUFFIX ub
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#define SDATA_TYPE int8_t
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#define DATA_TYPE uint8_t
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#else
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#error unsupported data size
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#endif
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/* For the benefit of TCG generated code, we want to avoid the complication
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of ABI-specific return type promotion and always return a value extended
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to the register size of the host. This is tcg_target_long, except in the
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case of a 32-bit host and 64-bit data, and for that we always have
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uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
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#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
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# define WORD_TYPE DATA_TYPE
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# define USUFFIX SUFFIX
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#else
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# define WORD_TYPE tcg_target_ulong
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# define USUFFIX glue(u, SUFFIX)
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# define SSUFFIX glue(s, SUFFIX)
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#endif
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#ifdef SOFTMMU_CODE_ACCESS
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#define READ_ACCESS_TYPE MMU_INST_FETCH
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#define ADDR_READ addr_code
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#else
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#define READ_ACCESS_TYPE MMU_DATA_LOAD
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#define ADDR_READ addr_read
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#endif
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#if DATA_SIZE == 8
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# define BSWAP(X) bswap64(X)
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#elif DATA_SIZE == 4
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# define BSWAP(X) bswap32(X)
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#elif DATA_SIZE == 2
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# define BSWAP(X) bswap16(X)
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#else
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# define BSWAP(X) (X)
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#endif
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#if DATA_SIZE == 1
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# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
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# define helper_be_ld_name helper_le_ld_name
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# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
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# define helper_be_lds_name helper_le_lds_name
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# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
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# define helper_be_st_name helper_le_st_name
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#else
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# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
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# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
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# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
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# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
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# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
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# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
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#endif
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#ifndef SOFTMMU_CODE_ACCESS
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static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
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size_t mmu_idx, size_t index,
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target_ulong addr,
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uintptr_t retaddr,
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bool recheck,
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MMUAccessType access_type)
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{
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck,
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access_type, DATA_SIZE);
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}
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#endif
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WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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uintptr_t mmu_idx = get_mmuidx(oi);
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uintptr_t index = tlb_index(env, mmu_idx, addr);
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CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
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target_ulong tlb_addr = entry->ADDR_READ;
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unsigned a_bits = get_alignment_bits(get_memop(oi));
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uintptr_t haddr;
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DATA_TYPE res;
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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/* If the TLB entry is for a different page, reload and try again. */
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if (!tlb_hit(tlb_addr, addr)) {
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if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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tlb_addr = entry->ADDR_READ;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr,
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tlb_addr & TLB_RECHECK,
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READ_ACCESS_TYPE);
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res = TGT_LE(res);
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return res;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
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DATA_TYPE res1, res2;
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unsigned shift;
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do_unaligned_access:
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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res1 = helper_le_ld_name(env, addr1, oi, retaddr);
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res2 = helper_le_ld_name(env, addr2, oi, retaddr);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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/* Little-endian combine. */
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res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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return res;
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}
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haddr = addr + entry->addend;
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#if DATA_SIZE == 1
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res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
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#else
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res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
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#endif
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return res;
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}
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#if DATA_SIZE > 1
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WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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uintptr_t mmu_idx = get_mmuidx(oi);
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uintptr_t index = tlb_index(env, mmu_idx, addr);
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CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
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target_ulong tlb_addr = entry->ADDR_READ;
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unsigned a_bits = get_alignment_bits(get_memop(oi));
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uintptr_t haddr;
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DATA_TYPE res;
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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/* If the TLB entry is for a different page, reload and try again. */
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if (!tlb_hit(tlb_addr, addr)) {
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if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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tlb_addr = entry->ADDR_READ;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr,
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tlb_addr & TLB_RECHECK,
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READ_ACCESS_TYPE);
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res = TGT_BE(res);
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return res;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
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DATA_TYPE res1, res2;
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unsigned shift;
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do_unaligned_access:
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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res1 = helper_be_ld_name(env, addr1, oi, retaddr);
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res2 = helper_be_ld_name(env, addr2, oi, retaddr);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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/* Big-endian combine. */
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res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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return res;
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}
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haddr = addr + entry->addend;
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res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
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return res;
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}
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#endif /* DATA_SIZE > 1 */
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#ifndef SOFTMMU_CODE_ACCESS
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/* Provide signed versions of the load routines as well. We can of course
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avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
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#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
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WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr);
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}
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# if DATA_SIZE > 1
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WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr);
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}
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# endif
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#endif
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static inline void glue(io_write, SUFFIX)(CPUArchState *env,
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size_t mmu_idx, size_t index,
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DATA_TYPE val,
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target_ulong addr,
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uintptr_t retaddr,
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bool recheck)
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{
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr,
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recheck, DATA_SIZE);
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}
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void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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uintptr_t mmu_idx = get_mmuidx(oi);
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uintptr_t index = tlb_index(env, mmu_idx, addr);
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CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
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target_ulong tlb_addr = entry->addr_write;
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unsigned a_bits = get_alignment_bits(get_memop(oi));
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uintptr_t haddr;
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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/* If the TLB entry is for a different page, reload and try again. */
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if (!tlb_hit(tlb_addr, addr)) {
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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tlb_addr = entry->addr_write & ~TLB_INVALID_MASK;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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val = TGT_LE(val);
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glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr,
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retaddr, tlb_addr & TLB_RECHECK);
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return;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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int i;
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target_ulong page2;
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CPUTLBEntry *entry2;
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do_unaligned_access:
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/* Ensure the second page is in the TLB. Note that the first page
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is already guaranteed to be filled, and that the second page
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cannot evict the first. */
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page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
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entry2 = tlb_entry(env, mmu_idx, page2);
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if (!tlb_hit_page(entry2->addr_write, page2)
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&& !VICTIM_TLB_HIT(addr_write, page2)) {
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tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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/* XXX: not efficient, but simple. */
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/* This loop must go in the forward direction to avoid issues
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with self-modifying code in Windows 64-bit. */
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for (i = 0; i < DATA_SIZE; ++i) {
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/* Little-endian extract. */
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uint8_t val8 = val >> (i * 8);
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glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
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oi, retaddr);
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}
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return;
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}
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haddr = addr + entry->addend;
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#if DATA_SIZE == 1
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glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
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#else
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glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
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#endif
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}
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#if DATA_SIZE > 1
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void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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uintptr_t mmu_idx = get_mmuidx(oi);
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uintptr_t index = tlb_index(env, mmu_idx, addr);
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CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
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target_ulong tlb_addr = entry->addr_write;
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unsigned a_bits = get_alignment_bits(get_memop(oi));
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uintptr_t haddr;
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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/* If the TLB entry is for a different page, reload and try again. */
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if (!tlb_hit(tlb_addr, addr)) {
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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tlb_addr = entry->addr_write & ~TLB_INVALID_MASK;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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val = TGT_BE(val);
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glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr,
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tlb_addr & TLB_RECHECK);
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return;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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int i;
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target_ulong page2;
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CPUTLBEntry *entry2;
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do_unaligned_access:
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/* Ensure the second page is in the TLB. Note that the first page
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is already guaranteed to be filled, and that the second page
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cannot evict the first. */
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page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
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entry2 = tlb_entry(env, mmu_idx, page2);
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if (!tlb_hit_page(entry2->addr_write, page2)
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&& !VICTIM_TLB_HIT(addr_write, page2)) {
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tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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/* XXX: not efficient, but simple */
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/* This loop must go in the forward direction to avoid issues
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with self-modifying code. */
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for (i = 0; i < DATA_SIZE; ++i) {
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/* Big-endian extract. */
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uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
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glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
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oi, retaddr);
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}
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return;
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}
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haddr = addr + entry->addend;
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glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
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}
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#endif /* DATA_SIZE > 1 */
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#endif /* !defined(SOFTMMU_CODE_ACCESS) */
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#undef READ_ACCESS_TYPE
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#undef DATA_TYPE
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#undef SUFFIX
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#undef LSUFFIX
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#undef DATA_SIZE
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#undef ADDR_READ
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#undef WORD_TYPE
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#undef SDATA_TYPE
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#undef USUFFIX
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#undef SSUFFIX
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#undef BSWAP
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#undef helper_le_ld_name
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#undef helper_be_ld_name
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#undef helper_le_lds_name
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#undef helper_be_lds_name
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#undef helper_le_st_name
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#undef helper_be_st_name
|