0b8fa32f55
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-4-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for hw/usb/dev-hub.c hw/misc/exynos4210_rng.c hw/misc/bcm2835_rng.c hw/misc/aspeed_scu.c hw/display/virtio-vga.c hw/arm/stm32f205_soc.c; ui/cocoa.m fixed up]
543 lines
17 KiB
C
543 lines
17 KiB
C
/*
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* QEMU Ultrasparc Sabre PCI host (PBM)
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2012,2013 Artyom Tarasenko
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* Copyright (c) 2018 Mark Cave-Ayland
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci-bridge/simba.h"
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#include "hw/pci-host/sabre.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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/*
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* Chipset docs:
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* PBM: "UltraSPARC IIi User's Manual",
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* http://www.sun.com/processors/manuals/805-0087.pdf
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*/
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#define PBM_PCI_IMR_MASK 0x7fffffff
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#define PBM_PCI_IMR_ENABLED 0x80000000
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#define POR (1U << 31)
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#define SOFT_POR (1U << 30)
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#define SOFT_XIR (1U << 29)
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#define BTN_POR (1U << 28)
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#define BTN_XIR (1U << 27)
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#define RESET_MASK 0xf8000000
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#define RESET_WCMASK 0x98000000
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#define RESET_WMASK 0x60000000
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#define NO_IRQ_REQUEST (MAX_IVEC + 1)
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static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
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{
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trace_sabre_set_request(irq_num);
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s->irq_request = irq_num;
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qemu_set_irq(s->ivec_irqs[irq_num], 1);
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}
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static inline void sabre_check_irqs(SabreState *s)
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{
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unsigned int i;
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/* Previous request is not acknowledged, resubmit */
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if (s->irq_request != NO_IRQ_REQUEST) {
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sabre_set_request(s, s->irq_request);
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return;
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}
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/* no request pending */
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if (s->pci_irq_in == 0ULL) {
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return;
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}
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for (i = 0; i < 32; i++) {
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if (s->pci_irq_in & (1ULL << i)) {
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if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
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sabre_set_request(s, i);
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return;
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}
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}
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}
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for (i = 32; i < 64; i++) {
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if (s->pci_irq_in & (1ULL << i)) {
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if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
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sabre_set_request(s, i);
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break;
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}
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}
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}
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}
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static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
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{
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trace_sabre_clear_request(irq_num);
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qemu_set_irq(s->ivec_irqs[irq_num], 0);
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s->irq_request = NO_IRQ_REQUEST;
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}
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static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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{
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IOMMUState *is = opaque;
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return &is->iommu_as;
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}
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static void sabre_config_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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SabreState *s = opaque;
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trace_sabre_config_write(addr, val);
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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/* XXX: not implemented yet */
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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unsigned int ino = (addr & 0x3f) >> 3;
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s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
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if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
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sabre_clear_request(s, ino);
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}
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sabre_check_irqs(s);
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}
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break;
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case 0x1000 ... 0x107f: /* OBIO interrupt control */
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if (addr & 4) {
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unsigned int ino = ((addr & 0xff) >> 3);
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s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
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s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
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if ((s->irq_request == (ino | 0x20))
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&& !(val & ~PBM_PCI_IMR_MASK)) {
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sabre_clear_request(s, ino | 0x20);
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}
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sabre_check_irqs(s);
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}
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break;
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case 0x1400 ... 0x14ff: /* PCI interrupt clear */
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if (addr & 4) {
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unsigned int ino = (addr & 0xff) >> 5;
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if ((s->irq_request / 4) == ino) {
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sabre_clear_request(s, s->irq_request);
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sabre_check_irqs(s);
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}
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}
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break;
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case 0x1800 ... 0x1860: /* OBIO interrupt clear */
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if (addr & 4) {
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unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
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if (s->irq_request == ino) {
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sabre_clear_request(s, ino);
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sabre_check_irqs(s);
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}
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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s->pci_control[(addr & 0x3f) >> 2] = val;
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break;
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case 0xf020 ... 0xf027: /* Reset control */
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if (addr & 4) {
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val &= RESET_MASK;
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s->reset_control &= ~(val & RESET_WCMASK);
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s->reset_control |= val & RESET_WMASK;
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if (val & SOFT_POR) {
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s->nr_resets = 0;
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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} else if (val & SOFT_XIR) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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}
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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case 0xf000 ... 0xf01f: /* FFB config, memory control */
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/* we don't care */
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default:
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break;
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}
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}
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static uint64_t sabre_config_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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SabreState *s = opaque;
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uint32_t val;
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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val = 0;
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/* XXX: not implemented yet */
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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val = s->pci_irq_map[(addr & 0x3f) >> 3];
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} else {
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val = 0;
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}
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break;
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case 0x1000 ... 0x107f: /* OBIO interrupt control */
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if (addr & 4) {
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val = s->obio_irq_map[(addr & 0xff) >> 3];
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} else {
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val = 0;
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}
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break;
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case 0x1080 ... 0x108f: /* PCI bus error */
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if (addr & 4) {
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val = s->pci_err_irq_map[(addr & 0xf) >> 3];
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} else {
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val = 0;
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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val = s->pci_control[(addr & 0x3f) >> 2];
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break;
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case 0xf020 ... 0xf027: /* Reset control */
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if (addr & 4) {
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val = s->reset_control;
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} else {
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val = 0;
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}
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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case 0xf000 ... 0xf01f: /* FFB config, memory control */
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/* we don't care */
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default:
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val = 0;
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break;
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}
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trace_sabre_config_read(addr, val);
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return val;
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}
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static const MemoryRegionOps sabre_config_ops = {
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.read = sabre_config_read,
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.write = sabre_config_write,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void sabre_pci_config_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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SabreState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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trace_sabre_pci_config_write(addr, val);
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pci_data_write(phb->bus, addr, val, size);
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}
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static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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uint32_t ret;
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SabreState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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ret = pci_data_read(phb->bus, addr, size);
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trace_sabre_pci_config_read(addr, ret);
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return ret;
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}
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/* The sabre host has an IRQ line for each IRQ line of each slot. */
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static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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/* Return the irq as swizzled by the PBM */
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return irq_num;
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}
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static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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/* The on-board devices have fixed (legacy) OBIO intnos */
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switch (PCI_SLOT(pci_dev->devfn)) {
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case 1:
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/* Onboard NIC */
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return OBIO_NIC_IRQ;
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case 3:
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/* Onboard IDE */
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return OBIO_HDD_IRQ;
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default:
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/* Normal intno, fall through */
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break;
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}
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return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
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}
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static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
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}
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static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
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{
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SabreState *s = opaque;
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trace_sabre_pci_set_irq(irq_num, level);
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/* PCI IRQ map onto the first 32 INO. */
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if (irq_num < 32) {
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if (level) {
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s->pci_irq_in |= 1ULL << irq_num;
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if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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sabre_set_request(s, irq_num);
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}
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} else {
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s->pci_irq_in &= ~(1ULL << irq_num);
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}
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} else {
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/* OBIO IRQ map onto the next 32 INO. */
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if (level) {
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trace_sabre_pci_set_obio_irq(irq_num, level);
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s->pci_irq_in |= 1ULL << irq_num;
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if ((s->irq_request == NO_IRQ_REQUEST)
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&& (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
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sabre_set_request(s, irq_num);
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}
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} else {
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s->pci_irq_in &= ~(1ULL << irq_num);
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}
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}
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}
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static void sabre_reset(DeviceState *d)
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{
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SabreState *s = SABRE_DEVICE(d);
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PCIDevice *pci_dev;
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unsigned int i;
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uint16_t cmd;
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
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}
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for (i = 0; i < 32; i++) {
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s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
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}
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s->irq_request = NO_IRQ_REQUEST;
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s->pci_irq_in = 0ULL;
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if (s->nr_resets++ == 0) {
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/* Power on reset */
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s->reset_control = POR;
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}
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/* As this is the busA PCI bridge which contains the on-board devices
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* attached to the ebus, ensure that we initially allow IO transactions
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* so that we get the early serial console until OpenBIOS can properly
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* configure the PCI bridge itself */
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pci_dev = PCI_DEVICE(s->bridgeA);
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cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
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pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO);
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pci_bridge_update_mappings(PCI_BRIDGE(pci_dev));
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}
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static const MemoryRegionOps pci_config_ops = {
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.read = sabre_pci_config_read,
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.write = sabre_pci_config_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void sabre_realize(DeviceState *dev, Error **errp)
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{
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SabreState *s = SABRE_DEVICE(dev);
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PCIHostState *phb = PCI_HOST_BRIDGE(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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PCIDevice *pci_dev;
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/* sabre_config */
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sysbus_mmio_map(sbd, 0, s->special_base);
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/* PCI configuration space */
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sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
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/* pci_ioport */
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sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL);
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memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
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memory_region_add_subregion(get_system_memory(), s->mem_base,
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&s->pci_mmio);
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phb->bus = pci_register_root_bus(dev, "pci",
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pci_sabre_set_irq, pci_sabre_map_irq, s,
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&s->pci_mmio,
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&s->pci_ioport,
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0, 32, TYPE_PCI_BUS);
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pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
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/* IOMMU */
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memory_region_add_subregion_overlap(&s->sabre_config, 0x200,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
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pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
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/* APB secondary busses */
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
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TYPE_SIMBA_PCI_BRIDGE);
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s->bridgeB = PCI_BRIDGE(pci_dev);
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pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq);
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qdev_init_nofail(&pci_dev->qdev);
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
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TYPE_SIMBA_PCI_BRIDGE);
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s->bridgeA = PCI_BRIDGE(pci_dev);
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pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq);
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qdev_init_nofail(&pci_dev->qdev);
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}
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static void sabre_init(Object *obj)
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{
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SabreState *s = SABRE_DEVICE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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unsigned int i;
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
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}
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for (i = 0; i < 2; i++) {
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s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
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}
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for (i = 0; i < 32; i++) {
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s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
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}
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qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC);
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qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC);
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s->irq_request = NO_IRQ_REQUEST;
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s->pci_irq_in = 0ULL;
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/* IOMMU */
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object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU,
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(Object **) &s->iommu,
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qdev_prop_allow_set_link_before_realize,
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0, NULL);
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/* sabre_config */
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memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
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"sabre-config", 0x10000);
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/* at region 0 */
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sysbus_init_mmio(sbd, &s->sabre_config);
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memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
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"sabre-pci-config", 0x1000000);
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/* at region 1 */
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sysbus_init_mmio(sbd, &s->pci_config);
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/* pci_ioport */
|
|
memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport",
|
|
0x1000000);
|
|
|
|
/* at region 2 */
|
|
sysbus_init_mmio(sbd, &s->pci_ioport);
|
|
}
|
|
|
|
static void sabre_pci_realize(PCIDevice *d, Error **errp)
|
|
{
|
|
pci_set_word(d->config + PCI_COMMAND,
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
pci_set_word(d->config + PCI_STATUS,
|
|
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
|
|
PCI_STATUS_DEVSEL_MEDIUM);
|
|
}
|
|
|
|
static void sabre_pci_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
k->realize = sabre_pci_realize;
|
|
k->vendor_id = PCI_VENDOR_ID_SUN;
|
|
k->device_id = PCI_DEVICE_ID_SUN_SABRE;
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
|
/*
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
*/
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo sabre_pci_info = {
|
|
.name = TYPE_SABRE_PCI_DEVICE,
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(SabrePCIState),
|
|
.class_init = sabre_pci_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{ },
|
|
},
|
|
};
|
|
|
|
static char *sabre_ofw_unit_address(const SysBusDevice *dev)
|
|
{
|
|
SabreState *s = SABRE_DEVICE(dev);
|
|
|
|
return g_strdup_printf("%x,%x",
|
|
(uint32_t)((s->special_base >> 32) & 0xffffffff),
|
|
(uint32_t)(s->special_base & 0xffffffff));
|
|
}
|
|
|
|
static Property sabre_properties[] = {
|
|
DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0),
|
|
DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void sabre_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
dc->realize = sabre_realize;
|
|
dc->reset = sabre_reset;
|
|
dc->props = sabre_properties;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
dc->fw_name = "pci";
|
|
sbc->explicit_ofw_unit_address = sabre_ofw_unit_address;
|
|
}
|
|
|
|
static const TypeInfo sabre_info = {
|
|
.name = TYPE_SABRE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(SabreState),
|
|
.instance_init = sabre_init,
|
|
.class_init = sabre_class_init,
|
|
};
|
|
|
|
static void sabre_register_types(void)
|
|
{
|
|
type_register_static(&sabre_info);
|
|
type_register_static(&sabre_pci_info);
|
|
}
|
|
|
|
type_init(sabre_register_types)
|