235 lines
8.0 KiB
C
235 lines
8.0 KiB
C
/*
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* x86 gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#ifdef TARGET_X86_64
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static const int gpr_map[16] = {
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R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
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8, 9, 10, 11, 12, 13, 14, 15
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};
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#else
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#define gpr_map gpr_map32
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#endif
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static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
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#define IDX_IP_REG CPU_NB_REGS
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#define IDX_FLAGS_REG (IDX_IP_REG + 1)
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#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
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#define IDX_FP_REGS (IDX_SEG_REGS + 6)
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#define IDX_XMM_REGS (IDX_FP_REGS + 16)
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#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
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int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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if (n < CPU_NB_REGS) {
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if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
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return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
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} else if (n < CPU_NB_REGS32) {
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return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
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}
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} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
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#ifdef USE_X86LDOUBLE
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/* FIXME: byteswap float values - after fixing fpregs layout. */
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memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
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#else
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memset(mem_buf, 0, 10);
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#endif
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return 10;
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} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
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n -= IDX_XMM_REGS;
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if (n < CPU_NB_REGS32 ||
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(TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
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stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
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stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
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return 16;
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}
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} else {
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switch (n) {
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case IDX_IP_REG:
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if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
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return gdb_get_reg64(mem_buf, env->eip);
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} else {
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return gdb_get_reg32(mem_buf, env->eip);
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}
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case IDX_FLAGS_REG:
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return gdb_get_reg32(mem_buf, env->eflags);
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case IDX_SEG_REGS:
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return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
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case IDX_SEG_REGS + 1:
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return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
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case IDX_SEG_REGS + 2:
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return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
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case IDX_SEG_REGS + 3:
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return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
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case IDX_SEG_REGS + 4:
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return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
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case IDX_SEG_REGS + 5:
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return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
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case IDX_FP_REGS + 8:
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return gdb_get_reg32(mem_buf, env->fpuc);
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case IDX_FP_REGS + 9:
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return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
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(env->fpstt & 0x7) << 11);
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case IDX_FP_REGS + 10:
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return gdb_get_reg32(mem_buf, 0); /* ftag */
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case IDX_FP_REGS + 11:
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return gdb_get_reg32(mem_buf, 0); /* fiseg */
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case IDX_FP_REGS + 12:
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return gdb_get_reg32(mem_buf, 0); /* fioff */
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case IDX_FP_REGS + 13:
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return gdb_get_reg32(mem_buf, 0); /* foseg */
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case IDX_FP_REGS + 14:
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return gdb_get_reg32(mem_buf, 0); /* fooff */
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case IDX_FP_REGS + 15:
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return gdb_get_reg32(mem_buf, 0); /* fop */
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case IDX_MXCSR_REG:
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return gdb_get_reg32(mem_buf, env->mxcsr);
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}
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}
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return 0;
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}
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static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf)
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{
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CPUX86State *env = &cpu->env;
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uint16_t selector = ldl_p(mem_buf);
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if (selector != env->segs[sreg].selector) {
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#if defined(CONFIG_USER_ONLY)
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cpu_x86_load_seg(env, sreg, selector);
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#else
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unsigned int limit, flags;
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target_ulong base;
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if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
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int dpl = (env->eflags & VM_MASK) ? 3 : 0;
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base = selector << 4;
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limit = 0xffff;
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flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
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} else {
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if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
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&flags)) {
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return 4;
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}
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}
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cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
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#endif
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}
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return 4;
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}
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int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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uint32_t tmp;
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if (n < CPU_NB_REGS) {
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if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
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env->regs[gpr_map[n]] = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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} else if (n < CPU_NB_REGS32) {
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n = gpr_map32[n];
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env->regs[n] &= ~0xffffffffUL;
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env->regs[n] |= (uint32_t)ldl_p(mem_buf);
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return 4;
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}
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} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
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#ifdef USE_X86LDOUBLE
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/* FIXME: byteswap float values - after fixing fpregs layout. */
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memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
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#endif
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return 10;
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} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
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n -= IDX_XMM_REGS;
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if (n < CPU_NB_REGS32 ||
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(TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
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env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
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env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
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return 16;
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}
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} else {
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switch (n) {
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case IDX_IP_REG:
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if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
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env->eip = ldq_p(mem_buf);
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return 8;
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} else {
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env->eip &= ~0xffffffffUL;
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env->eip |= (uint32_t)ldl_p(mem_buf);
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return 4;
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}
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case IDX_FLAGS_REG:
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env->eflags = ldl_p(mem_buf);
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return 4;
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case IDX_SEG_REGS:
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return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
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case IDX_SEG_REGS + 1:
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return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
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case IDX_SEG_REGS + 2:
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return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
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case IDX_SEG_REGS + 3:
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return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
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case IDX_SEG_REGS + 4:
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return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
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case IDX_SEG_REGS + 5:
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return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
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case IDX_FP_REGS + 8:
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cpu_set_fpuc(env, ldl_p(mem_buf));
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return 4;
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case IDX_FP_REGS + 9:
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tmp = ldl_p(mem_buf);
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env->fpstt = (tmp >> 11) & 7;
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env->fpus = tmp & ~0x3800;
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return 4;
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case IDX_FP_REGS + 10: /* ftag */
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return 4;
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case IDX_FP_REGS + 11: /* fiseg */
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return 4;
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case IDX_FP_REGS + 12: /* fioff */
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return 4;
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case IDX_FP_REGS + 13: /* foseg */
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return 4;
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case IDX_FP_REGS + 14: /* fooff */
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return 4;
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case IDX_FP_REGS + 15: /* fop */
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return 4;
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case IDX_MXCSR_REG:
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cpu_set_mxcsr(env, ldl_p(mem_buf));
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return 4;
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}
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}
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/* Unrecognised register. */
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return 0;
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}
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