qemu/target
Peter Maydell 268b1b3dfb target/arm: Allow user-mode code to write CPSR.E via MSR
Using the MSR instruction to write to CPSR.E is deprecated, but it is
required to work from any mode including unprivileged code.  We were
incorrectly forbidding usermode code from writing it because
CPSR_USER did not include the CPSR_E bit.

We use CPSR_USER in only three places:
 * as the mask of what to allow userspace MSR to write to CPSR
 * when deciding what bits a linux-user signal-return should be
   able to write from the sigcontext structure
 * in target_user_copy_regs() when we set up the initial
   registers for the linux-user process

In the first two cases not being able to update CPSR.E is a bug, and
in the third case it doesn't matter because CPSR.E is always 0 there.
So we can fix both bugs by adding CPSR_E to CPSR_USER.

Because the cpsr_write() in restore_sigcontext() is now changing
a CPSR bit which is cached in hflags, we need to add an
arm_rebuild_hflags() call there; the callsite in
target_user_copy_regs() was already rebuilding hflags for other
reasons.

(The recommended way to change CPSR.E is to use the 'SETEND'
instruction, which we do correctly allow from usermode code.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200518142801.20503-1-peter.maydell@linaro.org
2020-05-21 22:05:27 +01:00
..
alpha accel/tcg: Relax va restrictions on 64-bit guests 2020-05-15 15:25:16 +01:00
arm target/arm: Allow user-mode code to write CPSR.E via MSR 2020-05-21 22:05:27 +01:00
cris x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
hppa softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
i386 softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
lm32 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
m68k softfloat: Name rounding mode enum 2020-05-19 08:41:26 -07:00
microblaze target/microblaze: monitor: Increase the number of registers reported 2020-05-14 16:01:02 +02:00
mips softfloat: Replace flag with bool 2020-05-19 08:40:50 -07:00
moxie cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
nios2 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
openrisc softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
ppc softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
riscv target/riscv: Add a sifive-e34 cpu type 2020-04-29 13:16:37 -07:00
rx target/rx/translate: Add missing fall through comment 2020-04-07 18:45:54 -07:00
s390x softfloat: Inline float64 compare specializations 2020-05-19 08:42:45 -07:00
sh4 gdbstub: Introduce gdb_get_float32() to get 32-bit float registers 2020-04-15 11:38:23 +01:00
sparc softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
tilegx cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
tricore cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
unicore32 softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
xtensa softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00