36778660d7
CPUPPCState includes fields htab_base and htab_mask which store the base address (GPA) and size (as a mask) of the guest's hashed page table (HPT). These are set when the SDR1 register is updated. Keeping these in sync with the SDR1 is actually a little bit fiddly, and probably not useful for performance, since keeping them expands the size of CPUPPCState. It also makes some upcoming changes harder to implement. This patch removes these fields, in favour of calculating them directly from the SDR1 contents when necessary. This does make a change to the behaviour of attempting to write a bad value (invalid HPT size) to the SDR1 with an mtspr instruction. Previously, the bad value would be stored in SDR1 and could be retrieved with a later mfspr, but the HPT size as used by the softmmu would be, clamped to the allowed values. Now, writing a bad value is treated as a no-op. An error message is printed in both new and old versions. I'm not sure which behaviour, if either, matches real hardware. I don't think it matters that much, since it's pretty clear that if an OS writes a bad value to SDR1, it's not going to boot. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
619 lines
18 KiB
C
619 lines
18 KiB
C
#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "sysemu/kvm.h"
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#include "helper_regs.h"
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#include "mmu-hash64.h"
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#include "migration/cpu.h"
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static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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unsigned int i, j;
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target_ulong sdr1;
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uint32_t fpscr;
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target_ulong xer;
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for (i = 0; i < 32; i++)
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qemu_get_betls(f, &env->gpr[i]);
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#if !defined(TARGET_PPC64)
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for (i = 0; i < 32; i++)
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qemu_get_betls(f, &env->gprh[i]);
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#endif
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qemu_get_betls(f, &env->lr);
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qemu_get_betls(f, &env->ctr);
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for (i = 0; i < 8; i++)
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qemu_get_be32s(f, &env->crf[i]);
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qemu_get_betls(f, &xer);
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cpu_write_xer(env, xer);
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qemu_get_betls(f, &env->reserve_addr);
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qemu_get_betls(f, &env->msr);
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for (i = 0; i < 4; i++)
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qemu_get_betls(f, &env->tgpr[i]);
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for (i = 0; i < 32; i++) {
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union {
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float64 d;
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uint64_t l;
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} u;
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u.l = qemu_get_be64(f);
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env->fpr[i] = u.d;
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}
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qemu_get_be32s(f, &fpscr);
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env->fpscr = fpscr;
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qemu_get_sbe32s(f, &env->access_type);
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#if defined(TARGET_PPC64)
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qemu_get_betls(f, &env->spr[SPR_ASR]);
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qemu_get_sbe32s(f, &env->slb_nr);
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#endif
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qemu_get_betls(f, &sdr1);
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for (i = 0; i < 32; i++)
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qemu_get_betls(f, &env->sr[i]);
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for (i = 0; i < 2; i++)
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for (j = 0; j < 8; j++)
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qemu_get_betls(f, &env->DBAT[i][j]);
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for (i = 0; i < 2; i++)
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for (j = 0; j < 8; j++)
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qemu_get_betls(f, &env->IBAT[i][j]);
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qemu_get_sbe32s(f, &env->nb_tlb);
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qemu_get_sbe32s(f, &env->tlb_per_way);
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qemu_get_sbe32s(f, &env->nb_ways);
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qemu_get_sbe32s(f, &env->last_way);
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qemu_get_sbe32s(f, &env->id_tlbs);
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qemu_get_sbe32s(f, &env->nb_pids);
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if (env->tlb.tlb6) {
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// XXX assumes 6xx
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for (i = 0; i < env->nb_tlb; i++) {
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qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
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qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
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qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
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}
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}
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for (i = 0; i < 4; i++)
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qemu_get_betls(f, &env->pb[i]);
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for (i = 0; i < 1024; i++)
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qemu_get_betls(f, &env->spr[i]);
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if (!env->external_htab) {
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ppc_store_sdr1(env, sdr1);
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}
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qemu_get_be32s(f, &env->vscr);
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qemu_get_be64s(f, &env->spe_acc);
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qemu_get_be32s(f, &env->spe_fscr);
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qemu_get_betls(f, &env->msr_mask);
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qemu_get_be32s(f, &env->flags);
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qemu_get_sbe32s(f, &env->error_code);
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qemu_get_be32s(f, &env->pending_interrupts);
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qemu_get_be32s(f, &env->irq_input_state);
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for (i = 0; i < POWERPC_EXCP_NB; i++)
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qemu_get_betls(f, &env->excp_vectors[i]);
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qemu_get_betls(f, &env->excp_prefix);
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qemu_get_betls(f, &env->ivor_mask);
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qemu_get_betls(f, &env->ivpr_mask);
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qemu_get_betls(f, &env->hreset_vector);
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qemu_get_betls(f, &env->nip);
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qemu_get_betls(f, &env->hflags);
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qemu_get_betls(f, &env->hflags_nmsr);
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qemu_get_sbe32(f); /* Discard unused mmu_idx */
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qemu_get_sbe32(f); /* Discard unused power_mode */
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/* Recompute mmu indices */
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hreg_compute_mem_idx(env);
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return 0;
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}
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static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field)
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{
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ppc_avr_t *v = pv;
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v->u64[0] = qemu_get_be64(f);
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v->u64[1] = qemu_get_be64(f);
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return 0;
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}
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static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field,
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QJSON *vmdesc)
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{
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ppc_avr_t *v = pv;
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qemu_put_be64(f, v->u64[0]);
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qemu_put_be64(f, v->u64[1]);
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return 0;
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}
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static const VMStateInfo vmstate_info_avr = {
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.name = "avr",
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.get = get_avr,
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.put = put_avr,
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};
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#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
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VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
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#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
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VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
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static bool cpu_pre_2_8_migration(void *opaque, int version_id)
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{
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PowerPCCPU *cpu = opaque;
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return cpu->pre_2_8_migration;
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}
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static void cpu_pre_save(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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int i;
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uint64_t insns_compat_mask =
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PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB
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| PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES
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| PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES
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| PPC_FLOAT_STFIWX | PPC_FLOAT_EXT
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| PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ
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| PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC
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| PPC_64B | PPC_64BX | PPC_ALTIVEC
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| PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD;
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uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX
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| PPC2_PERM_ISA206 | PPC2_DIVE_ISA206
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| PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
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| PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
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| PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
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| PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM;
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env->spr[SPR_LR] = env->lr;
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env->spr[SPR_CTR] = env->ctr;
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env->spr[SPR_XER] = cpu_read_xer(env);
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#if defined(TARGET_PPC64)
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env->spr[SPR_CFAR] = env->cfar;
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#endif
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env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
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for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
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env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
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env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
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env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
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env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
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}
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for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
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env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
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env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
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env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
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env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
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}
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/* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
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if (cpu->pre_2_8_migration) {
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cpu->mig_msr_mask = env->msr_mask;
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cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
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cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
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cpu->mig_nb_BATs = env->nb_BATs;
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}
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}
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static int cpu_post_load(void *opaque, int version_id)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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int i;
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target_ulong msr;
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/*
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* We always ignore the source PVR. The user or management
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* software has to take care of running QEMU in a compatible mode.
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*/
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env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
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env->lr = env->spr[SPR_LR];
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env->ctr = env->spr[SPR_CTR];
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cpu_write_xer(env, env->spr[SPR_XER]);
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#if defined(TARGET_PPC64)
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env->cfar = env->spr[SPR_CFAR];
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#endif
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env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
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for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
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env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
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env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
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env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
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env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
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}
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for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
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env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
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env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
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env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
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env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
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}
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if (!env->external_htab) {
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ppc_store_sdr1(env, env->spr[SPR_SDR1]);
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}
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/* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
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msr = env->msr;
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env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
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ppc_store_msr(env, msr);
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hreg_compute_mem_idx(env);
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return 0;
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}
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static bool fpu_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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return (cpu->env.insns_flags & PPC_FLOAT);
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}
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static const VMStateDescription vmstate_fpu = {
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.name = "cpu/fpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = fpu_needed,
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.fields = (VMStateField[]) {
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VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
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VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
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VMSTATE_END_OF_LIST()
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},
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};
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static bool altivec_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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return (cpu->env.insns_flags & PPC_ALTIVEC);
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}
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static const VMStateDescription vmstate_altivec = {
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.name = "cpu/altivec",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = altivec_needed,
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.fields = (VMStateField[]) {
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VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
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VMSTATE_UINT32(env.vscr, PowerPCCPU),
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VMSTATE_END_OF_LIST()
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},
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};
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static bool vsx_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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return (cpu->env.insns_flags2 & PPC2_VSX);
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}
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static const VMStateDescription vmstate_vsx = {
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.name = "cpu/vsx",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = vsx_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
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VMSTATE_END_OF_LIST()
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},
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};
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#ifdef TARGET_PPC64
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/* Transactional memory state */
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static bool tm_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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return msr_ts;
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}
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static const VMStateDescription vmstate_tm = {
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.name = "cpu/tm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.needed = tm_needed,
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.fields = (VMStateField []) {
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VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
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VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
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VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
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VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
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VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
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VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
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VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
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VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
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VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
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VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
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VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
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VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
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VMSTATE_END_OF_LIST()
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},
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};
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#endif
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static bool sr_needed(void *opaque)
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{
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#ifdef TARGET_PPC64
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PowerPCCPU *cpu = opaque;
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return !(cpu->env.mmu_model & POWERPC_MMU_64);
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#else
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return true;
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#endif
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}
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static const VMStateDescription vmstate_sr = {
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.name = "cpu/sr",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = sr_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
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VMSTATE_END_OF_LIST()
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},
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};
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#ifdef TARGET_PPC64
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static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field)
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{
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ppc_slb_t *v = pv;
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v->esid = qemu_get_be64(f);
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v->vsid = qemu_get_be64(f);
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return 0;
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}
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static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field,
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QJSON *vmdesc)
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{
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ppc_slb_t *v = pv;
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qemu_put_be64(f, v->esid);
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qemu_put_be64(f, v->vsid);
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return 0;
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}
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static const VMStateInfo vmstate_info_slbe = {
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.name = "slbe",
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.get = get_slbe,
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.put = put_slbe,
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};
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#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
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VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
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#define VMSTATE_SLB_ARRAY(_f, _s, _n) \
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VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
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static bool slb_needed(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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/* We don't support any of the old segment table based 64-bit CPUs */
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return (cpu->env.mmu_model & POWERPC_MMU_64);
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}
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static int slb_post_load(void *opaque, int version_id)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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int i;
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/* We've pulled in the raw esid and vsid values from the migration
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* stream, but we need to recompute the page size pointers */
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for (i = 0; i < env->slb_nr; i++) {
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if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
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/* Migration source had bad values in its SLB */
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return -1;
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}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_slb = {
|
|
.name = "cpu/slb",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = slb_needed,
|
|
.post_load = slb_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
|
|
VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
#endif /* TARGET_PPC64 */
|
|
|
|
static const VMStateDescription vmstate_tlb6xx_entry = {
|
|
.name = "cpu/tlb6xx_entry",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
|
|
VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
|
|
VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static bool tlb6xx_needed(void *opaque)
|
|
{
|
|
PowerPCCPU *cpu = opaque;
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
return env->nb_tlb && (env->tlb_type == TLB_6XX);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_tlb6xx = {
|
|
.name = "cpu/tlb6xx",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = tlb6xx_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
|
|
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
|
|
env.nb_tlb,
|
|
vmstate_tlb6xx_entry,
|
|
ppc6xx_tlb_t),
|
|
VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_tlbemb_entry = {
|
|
.name = "cpu/tlbemb_entry",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(RPN, ppcemb_tlb_t),
|
|
VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
|
|
VMSTATE_UINTTL(PID, ppcemb_tlb_t),
|
|
VMSTATE_UINTTL(size, ppcemb_tlb_t),
|
|
VMSTATE_UINT32(prot, ppcemb_tlb_t),
|
|
VMSTATE_UINT32(attr, ppcemb_tlb_t),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static bool tlbemb_needed(void *opaque)
|
|
{
|
|
PowerPCCPU *cpu = opaque;
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
return env->nb_tlb && (env->tlb_type == TLB_EMB);
|
|
}
|
|
|
|
static bool pbr403_needed(void *opaque)
|
|
{
|
|
PowerPCCPU *cpu = opaque;
|
|
uint32_t pvr = cpu->env.spr[SPR_PVR];
|
|
|
|
return (pvr & 0xffff0000) == 0x00200000;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_pbr403 = {
|
|
.name = "cpu/pbr403",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = pbr403_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static const VMStateDescription vmstate_tlbemb = {
|
|
.name = "cpu/tlb6xx",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = tlbemb_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
|
|
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
|
|
env.nb_tlb,
|
|
vmstate_tlbemb_entry,
|
|
ppcemb_tlb_t),
|
|
/* 403 protection registers */
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
.subsections = (const VMStateDescription*[]) {
|
|
&vmstate_pbr403,
|
|
NULL
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_tlbmas_entry = {
|
|
.name = "cpu/tlbmas_entry",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(mas8, ppcmas_tlb_t),
|
|
VMSTATE_UINT32(mas1, ppcmas_tlb_t),
|
|
VMSTATE_UINT64(mas2, ppcmas_tlb_t),
|
|
VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static bool tlbmas_needed(void *opaque)
|
|
{
|
|
PowerPCCPU *cpu = opaque;
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
return env->nb_tlb && (env->tlb_type == TLB_MAS);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_tlbmas = {
|
|
.name = "cpu/tlbmas",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.needed = tlbmas_needed,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
|
|
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
|
|
env.nb_tlb,
|
|
vmstate_tlbmas_entry,
|
|
ppcmas_tlb_t),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
const VMStateDescription vmstate_ppc_cpu = {
|
|
.name = "cpu",
|
|
.version_id = 5,
|
|
.minimum_version_id = 5,
|
|
.minimum_version_id_old = 4,
|
|
.load_state_old = cpu_load_old,
|
|
.pre_save = cpu_pre_save,
|
|
.post_load = cpu_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
|
|
|
|
/* User mode architected state */
|
|
VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
|
|
#if !defined(TARGET_PPC64)
|
|
VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
|
|
#endif
|
|
VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
|
|
VMSTATE_UINTTL(env.nip, PowerPCCPU),
|
|
|
|
/* SPRs */
|
|
VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
|
|
VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
|
|
|
|
/* Reservation */
|
|
VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
|
|
|
|
/* Supervisor mode architected state */
|
|
VMSTATE_UINTTL(env.msr, PowerPCCPU),
|
|
|
|
/* Internal state */
|
|
VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
|
|
/* FIXME: access_type? */
|
|
|
|
/* Sanity checking */
|
|
VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
|
|
VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
|
|
VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
|
|
cpu_pre_2_8_migration),
|
|
VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
.subsections = (const VMStateDescription*[]) {
|
|
&vmstate_fpu,
|
|
&vmstate_altivec,
|
|
&vmstate_vsx,
|
|
&vmstate_sr,
|
|
#ifdef TARGET_PPC64
|
|
&vmstate_tm,
|
|
&vmstate_slb,
|
|
#endif /* TARGET_PPC64 */
|
|
&vmstate_tlb6xx,
|
|
&vmstate_tlbemb,
|
|
&vmstate_tlbmas,
|
|
NULL
|
|
}
|
|
};
|