qemu/target
Peter Maydell 470dd165d1 MIPS queue for June 9th, 2020
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJe37ZzAAoJENSXKoln91pl03oH/0bOnlYdWnOaw6Z0cVLAaqei
 ZRaW/T158VrNNuqqwVbUv5wtIo3EqFFfBFayaGat83leYw/C5fRVAi/2qgjDU7iy
 fW5AESIFcg1SQNu4bHdZLUE4nh7rknDNWcHbeK4qMll6P3wwAIv00Xiz2mrqF5tF
 v8vzWvgPE4xD5+aIH+HtLDTCrKYJ1NoC48AEmehYci2IkPvlQiqkGxu4Z3BATXxM
 L/JdsIAJ9UcIYaNtni01snAsYefLlY14VHN7CGDxNhAySGzDp44XzOMfszjmONTg
 EJhuHqIzEs44INgNkT322D61MK4W2k+PaMGP4ZYNJKo1J9qJ/+1UtK9ZhcC6fjg=
 =CCiQ
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-09-2020' into staging

MIPS queue for June 9th, 2020

# gpg: Signature made Tue 09 Jun 2020 17:18:59 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full]
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-jun-09-2020:
  target/mips: Enable hardware page table walker and CMGCR features for P5600
  target/mips: Add Loongson-3 CPU definition
  target/mips: fpu: Refactor conversion from ieee to mips exception flags
  target/mips: fpu: Name better paired-single variables
  target/mips: fpu: Remove now unused FLOAT_RINT macro
  target/mips: fpu: Demacro RINT.<D|S>
  target/mips: fpu: Remove now unused FLOAT_CLASS macro
  target/mips: fpu: Demacro CLASS.<D|S>
  target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros
  target/mips: fpu: Demacro NMSUB.<D|S|PS>
  target/mips: fpu: Demacro NMADD.<D|S|PS>
  target/mips: fpu: Demacro MSUB.<D|S|PS>
  target/mips: fpu: Demacro MADD.<D|S|PS>
  target/mips: fpu: Remove now unused macro FLOAT_BINOP
  target/mips: fpu: Demacro DIV.<D|S|PS>
  target/mips: fpu: Demacro MUL.<D|S|PS>
  target/mips: fpu: Demacro SUB.<D|S|PS>
  target/mips: fpu: Demacro ADD.<D|S|PS>
  mailmap: Change email address of Stefan Brankovic
  mailmap: Change email address of Filip Bozuta

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-11 13:07:34 +01:00
..
alpha accel/tcg: Relax va restrictions on 64-bit guests 2020-05-15 15:25:16 +01:00
arm target/arm: Use a non-overlapping group for misc control 2020-06-09 09:21:19 -07:00
cris x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
hppa softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
i386 linux-user pull request 20200605-v2 2020-06-08 11:04:57 +01:00
lm32 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
m68k target/m68k: implement opcode fetoxm1 2020-06-02 13:59:02 +02:00
microblaze target/microblaze: monitor: Increase the number of registers reported 2020-05-14 16:01:02 +02:00
mips target/mips: Enable hardware page table walker and CMGCR features for P5600 2020-06-09 17:32:45 +02:00
moxie cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
nios2 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
openrisc softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
ppc target/ppc: Use tcg_gen_gvec_rotlv 2020-06-02 08:42:37 -07:00
riscv linux-user pull request 20200605-v2 2020-06-08 11:04:57 +01:00
rx target/rx/translate: Add missing fall through comment 2020-04-07 18:45:54 -07:00
s390x linux-user pull request 20200605-v2 2020-06-08 11:04:57 +01:00
sh4 gdbstub: Introduce gdb_get_float32() to get 32-bit float registers 2020-04-15 11:38:23 +01:00
sparc target/sparc/int32_helper: Extract and use excp_name_str() 2020-06-09 09:21:10 +02:00
tilegx cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
tricore target/tricore: Implement gdbstub 2020-06-01 16:55:13 +02:00
unicore32 softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
xtensa softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00