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35b5c04427
qemu/target-xtensa
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Max Filippov 35b5c04427 target-xtensa: add ICOUNT SR and debug exception 
ICOUNT SR gets incremented on every instruction completion provided that
CINTLEVEL at the beginning of the instruction execution is lower than
ICOUNTLEVEL.

When ICOUNT would increment to 0 a debug exception is raised if
CINTLEVEL is lower than DEBUGLEVEL.

See ISA, 4.7.7.5 for more details.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18 14:55:52 +04:00
..
core-dc232b target-xtensa: add dc232b core 2011-10-16 10:40:02 +00:00
core-fsf target-xtensa: add fsf core 2011-10-16 10:40:16 +00:00
core-dc232b.c target-xtensa: add dc232b core 2011-10-16 10:40:02 +00:00
core-fsf.c target-xtensa: add fsf core 2011-10-16 10:40:16 +00:00
cpu.h target-xtensa: add ICOUNT SR and debug exception 2012-02-18 14:55:52 +04:00
helper.c target-xtensa: implement instruction breakpoints 2012-02-18 14:55:51 +04:00
helpers.h target-xtensa: implement instruction breakpoints 2012-02-18 14:55:51 +04:00
machine.c
op_helper.c target-xtensa: implement instruction breakpoints 2012-02-18 14:55:51 +04:00
overlay_tool.h target-xtensa: define TLB_TEMPLATE for MMU-less cores 2012-02-18 01:25:27 +04:00
translate.c target-xtensa: add ICOUNT SR and debug exception 2012-02-18 14:55:52 +04:00