Philippe Mathieu-Daudé 18f86aecd6 target/mips: Fix TX79 LQ/SQ opcodes ... The base register address offset is *signed*. Cc: qemu-stable@nongnu.org Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914090447.12557-1-philmd@linaro.org>		2023-11-07 12:13:28 +01:00
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sysemu
dsp_helper.c
exception.c
fpu_helper.c
lcsr_translate.c
lcsr.decode
ldst_helper.c
lmmi_helper.c
meson.build
micromips_translate.c.inc
mips16e_translate.c.inc
msa_helper.c
msa_helper.h.inc
msa_translate.c
msa.decode
mxu_translate.c
nanomips_translate.c.inc
octeon_translate.c
octeon.decode
op_helper.c
rel6_translate.c
rel6.decode
sysemu_helper.h.inc
tcg-internal.h
trace-events
trace.h
translate_addr_const.c
translate.c
translate.h
tx79_translate.c
tx79.decode	target/mips: Fix TX79 LQ/SQ opcodes	2023-11-07 12:13:28 +01:00
txx9_translate.c
vr54xx_helper.c
vr54xx_helper.h.inc
vr54xx_translate.c
vr54xx.decode