355b194369
Historically the qemu tlb "addend" field was used for both RAM and IO accesses, so needed to be able to hold both host addresses (unsigned long) and guest physical addresses (target_phys_addr_t). However since the introduction of the iotlb field it has only been used for RAM accesses. This means we can change the type of addend to unsigned long, and remove associated hacks in the big-endian TCG backends. We can also remove the host dependence from target_phys_addr_t. Signed-off-by: Paul Brook <paul@codesourcery.com>
1701 lines
47 KiB
C
1701 lines
47 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#define TCG_CT_CONST_U32 0x100
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static uint8_t *tb_ret_addr;
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#define FAST_PATH
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#if TARGET_LONG_BITS == 32
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#define LD_ADDR LWZU
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#define CMP_L 0
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#else
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#define LD_ADDR LDU
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#define CMP_L (1<<21)
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#endif
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#ifndef GUEST_BASE
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#define GUEST_BASE 0
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#endif
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#ifdef CONFIG_USE_GUEST_BASE
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#define TCG_GUEST_BASE_REG 30
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#else
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#define TCG_GUEST_BASE_REG 0
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#endif
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"r0",
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"r1",
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"rp",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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"r8",
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"r9",
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"r10",
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"r11",
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"r12",
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"r13",
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"r14",
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"r15",
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"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
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"r30",
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"r31"
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};
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#endif
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static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_R16,
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TCG_REG_R17,
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TCG_REG_R18,
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TCG_REG_R19,
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TCG_REG_R20,
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TCG_REG_R21,
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TCG_REG_R22,
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TCG_REG_R23,
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TCG_REG_R28,
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TCG_REG_R29,
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TCG_REG_R30,
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TCG_REG_R31,
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#ifdef __APPLE__
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TCG_REG_R2,
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#endif
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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#ifndef __APPLE__
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TCG_REG_R11,
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#endif
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TCG_REG_R12,
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TCG_REG_R24,
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TCG_REG_R25,
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TCG_REG_R26,
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TCG_REG_R27
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};
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static const int tcg_target_call_iarg_regs[] = {
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10
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};
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static const int tcg_target_call_oarg_regs[2] = {
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TCG_REG_R3
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};
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static const int tcg_target_callee_save_regs[] = {
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#ifdef __APPLE__
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TCG_REG_R11,
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#endif
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_R16,
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TCG_REG_R17,
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TCG_REG_R18,
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TCG_REG_R19,
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TCG_REG_R20,
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TCG_REG_R21,
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TCG_REG_R22,
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TCG_REG_R23,
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TCG_REG_R24,
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TCG_REG_R25,
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TCG_REG_R26,
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/* TCG_REG_R27, */ /* currently used for the global env, so no
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need to save */
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TCG_REG_R28,
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TCG_REG_R29,
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TCG_REG_R30,
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TCG_REG_R31
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};
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static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
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{
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tcg_target_long disp;
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disp = target - (tcg_target_long) pc;
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if ((disp << 38) >> 38 != disp)
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tcg_abort ();
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return disp & 0x3fffffc;
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}
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static void reloc_pc24 (void *pc, tcg_target_long target)
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{
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*(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
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| reloc_pc24_val (pc, target);
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}
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static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
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{
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tcg_target_long disp;
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disp = target - (tcg_target_long) pc;
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if (disp != (int16_t) disp)
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tcg_abort ();
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return disp & 0xfffc;
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}
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static void reloc_pc14 (void *pc, tcg_target_long target)
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{
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*(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
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| reloc_pc14_val (pc, target);
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}
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static void patch_reloc (uint8_t *code_ptr, int type,
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tcg_target_long value, tcg_target_long addend)
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{
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value += addend;
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switch (type) {
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case R_PPC_REL14:
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reloc_pc14 (code_ptr, value);
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break;
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case R_PPC_REL24:
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reloc_pc24 (code_ptr, value);
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break;
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default:
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tcg_abort ();
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}
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}
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/* maximum number of register used for input function arguments */
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static int tcg_target_get_call_iarg_regs_count (int flags)
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{
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return ARRAY_SIZE (tcg_target_call_iarg_regs);
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}
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/* parse target specific constraints */
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static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
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{
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const char *ct_str;
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ct_str = *pct_str;
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switch (ct_str[0]) {
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case 'A': case 'B': case 'C': case 'D':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
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break;
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case 'r':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
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break;
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case 'L': /* qemu_ld constraint */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
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#ifdef CONFIG_SOFTMMU
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
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#endif
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break;
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case 'S': /* qemu_st constraint */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
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#ifdef CONFIG_SOFTMMU
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
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tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
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#endif
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break;
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case 'Z':
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ct->ct |= TCG_CT_CONST_U32;
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break;
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default:
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return -1;
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}
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ct_str++;
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*pct_str = ct_str;
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return 0;
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}
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/* test if a constant matches the constraint */
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static int tcg_target_const_match (tcg_target_long val,
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const TCGArgConstraint *arg_ct)
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{
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int ct;
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ct = arg_ct->ct;
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if (ct & TCG_CT_CONST)
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return 1;
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else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
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return 1;
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return 0;
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}
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#define OPCD(opc) ((opc)<<26)
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#define XO19(opc) (OPCD(19)|((opc)<<1))
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#define XO30(opc) (OPCD(30)|((opc)<<2))
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#define XO31(opc) (OPCD(31)|((opc)<<1))
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#define XO58(opc) (OPCD(58)|(opc))
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#define XO62(opc) (OPCD(62)|(opc))
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#define B OPCD( 18)
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#define BC OPCD( 16)
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#define LBZ OPCD( 34)
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#define LHZ OPCD( 40)
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#define LHA OPCD( 42)
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#define LWZ OPCD( 32)
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#define STB OPCD( 38)
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#define STH OPCD( 44)
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#define STW OPCD( 36)
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#define STD XO62( 0)
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#define STDU XO62( 1)
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#define STDX XO31(149)
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#define LD XO58( 0)
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#define LDX XO31( 21)
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#define LDU XO58( 1)
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#define LWA XO58( 2)
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#define LWAX XO31(341)
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#define ADDIC OPCD( 12)
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#define ADDI OPCD( 14)
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#define ADDIS OPCD( 15)
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#define ORI OPCD( 24)
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#define ORIS OPCD( 25)
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#define XORI OPCD( 26)
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#define XORIS OPCD( 27)
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#define ANDI OPCD( 28)
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#define ANDIS OPCD( 29)
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#define MULLI OPCD( 7)
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#define CMPLI OPCD( 10)
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#define CMPI OPCD( 11)
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#define LWZU OPCD( 33)
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#define STWU OPCD( 37)
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#define RLWINM OPCD( 21)
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#define RLDICL XO30( 0)
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#define RLDICR XO30( 1)
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#define RLDIMI XO30( 3)
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#define BCLR XO19( 16)
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#define BCCTR XO19(528)
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#define CRAND XO19(257)
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#define CRANDC XO19(129)
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#define CRNAND XO19(225)
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#define CROR XO19(449)
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#define CRNOR XO19( 33)
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#define EXTSB XO31(954)
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#define EXTSH XO31(922)
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#define EXTSW XO31(986)
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#define ADD XO31(266)
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#define ADDE XO31(138)
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#define ADDC XO31( 10)
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#define AND XO31( 28)
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#define SUBF XO31( 40)
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#define SUBFC XO31( 8)
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#define SUBFE XO31(136)
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#define OR XO31(444)
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#define XOR XO31(316)
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#define MULLW XO31(235)
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#define MULHWU XO31( 11)
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#define DIVW XO31(491)
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#define DIVWU XO31(459)
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#define CMP XO31( 0)
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#define CMPL XO31( 32)
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#define LHBRX XO31(790)
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#define LWBRX XO31(534)
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#define STHBRX XO31(918)
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#define STWBRX XO31(662)
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#define MFSPR XO31(339)
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#define MTSPR XO31(467)
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#define SRAWI XO31(824)
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#define NEG XO31(104)
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#define MFCR XO31( 19)
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#define CNTLZW XO31( 26)
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#define CNTLZD XO31( 58)
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#define MULLD XO31(233)
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#define MULHD XO31( 73)
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#define MULHDU XO31( 9)
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#define DIVD XO31(489)
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#define DIVDU XO31(457)
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#define LBZX XO31( 87)
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#define LHZX XO31(279)
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#define LHAX XO31(343)
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#define LWZX XO31( 23)
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#define STBX XO31(215)
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#define STHX XO31(407)
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#define STWX XO31(151)
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#define SPR(a,b) ((((a)<<5)|(b))<<11)
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#define LR SPR(8, 0)
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#define CTR SPR(9, 0)
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#define SLW XO31( 24)
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#define SRW XO31(536)
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#define SRAW XO31(792)
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#define SLD XO31( 27)
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#define SRD XO31(539)
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#define SRAD XO31(794)
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#define SRADI XO31(413<<1)
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#define TW XO31( 4)
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#define TRAP (TW | TO (31))
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#define RT(r) ((r)<<21)
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#define RS(r) ((r)<<21)
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#define RA(r) ((r)<<16)
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#define RB(r) ((r)<<11)
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#define TO(t) ((t)<<21)
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#define SH(s) ((s)<<11)
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#define MB(b) ((b)<<6)
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#define ME(e) ((e)<<1)
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#define BO(o) ((o)<<21)
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#define MB64(b) ((b)<<5)
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#define LK 1
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#define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
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#define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
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#define BF(n) ((n)<<23)
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#define BI(n, c) (((c)+((n)*4))<<16)
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#define BT(n, c) (((c)+((n)*4))<<21)
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#define BA(n, c) (((c)+((n)*4))<<16)
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#define BB(n, c) (((c)+((n)*4))<<11)
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#define BO_COND_TRUE BO (12)
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#define BO_COND_FALSE BO ( 4)
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#define BO_ALWAYS BO (20)
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enum {
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CR_LT,
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CR_GT,
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CR_EQ,
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CR_SO
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};
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static const uint32_t tcg_to_bc[10] = {
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[TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
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[TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
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[TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
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[TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
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[TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
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[TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
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[TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
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[TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
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[TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
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[TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
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};
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static void tcg_out_mov (TCGContext *s, int ret, int arg)
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{
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tcg_out32 (s, OR | SAB (arg, ret, arg));
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}
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static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
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{
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sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
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mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
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tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
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}
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static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
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{
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if (arg == (int16_t) arg)
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tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
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else {
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tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
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if (arg & 0xffff)
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tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
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}
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}
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static void tcg_out_movi (TCGContext *s, TCGType type,
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int ret, tcg_target_long arg)
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{
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int32_t arg32 = arg;
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arg = type == TCG_TYPE_I32 ? arg & 0xffffffff : arg;
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if (arg == arg32) {
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tcg_out_movi32 (s, ret, arg32);
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}
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else {
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if ((uint64_t) arg >> 32) {
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uint16_t h16 = arg >> 16;
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uint16_t l16 = arg;
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tcg_out_movi32 (s, ret, arg >> 32);
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tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
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if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
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if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
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}
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else {
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tcg_out_movi32 (s, ret, arg32);
|
|
if (arg32 < 0)
|
|
tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
|
|
{
|
|
tcg_target_long disp;
|
|
|
|
disp = target - (tcg_target_long) s->code_ptr;
|
|
if ((disp << 38) >> 38 == disp)
|
|
tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
|
|
else {
|
|
tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
|
|
tcg_out32 (s, MTSPR | RS (0) | CTR);
|
|
tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
|
|
}
|
|
}
|
|
|
|
static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
|
|
{
|
|
#ifdef __APPLE__
|
|
if (const_arg) {
|
|
tcg_out_b (s, LK, arg);
|
|
}
|
|
else {
|
|
tcg_out32 (s, MTSPR | RS (arg) | LR);
|
|
tcg_out32 (s, BCLR | BO_ALWAYS | LK);
|
|
}
|
|
#else
|
|
int reg;
|
|
|
|
if (const_arg) {
|
|
reg = 2;
|
|
tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
|
|
}
|
|
else reg = arg;
|
|
|
|
tcg_out32 (s, LD | RT (0) | RA (reg));
|
|
tcg_out32 (s, MTSPR | RA (0) | CTR);
|
|
tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
|
|
tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
|
|
tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
|
|
#endif
|
|
}
|
|
|
|
static void tcg_out_ldst (TCGContext *s, int ret, int addr,
|
|
int offset, int op1, int op2)
|
|
{
|
|
if (offset == (int16_t) offset)
|
|
tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
|
|
else {
|
|
tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
|
|
tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
|
|
}
|
|
}
|
|
|
|
static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
|
|
int offset, int op1, int op2)
|
|
{
|
|
if (offset == (int16_t) (offset & ~3))
|
|
tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
|
|
else {
|
|
tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
|
|
tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
|
|
}
|
|
}
|
|
|
|
#if defined (CONFIG_SOFTMMU)
|
|
|
|
#include "../../softmmu_defs.h"
|
|
|
|
static void *qemu_ld_helpers[4] = {
|
|
__ldb_mmu,
|
|
__ldw_mmu,
|
|
__ldl_mmu,
|
|
__ldq_mmu,
|
|
};
|
|
|
|
static void *qemu_st_helpers[4] = {
|
|
__stb_mmu,
|
|
__stw_mmu,
|
|
__stl_mmu,
|
|
__stq_mmu,
|
|
};
|
|
|
|
static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
|
|
int addr_reg, int s_bits, int offset)
|
|
{
|
|
#if TARGET_LONG_BITS == 32
|
|
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
|
|
|
|
tcg_out32 (s, (RLWINM
|
|
| RA (r0)
|
|
| RS (addr_reg)
|
|
| SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
|
|
| MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
|
|
| ME (31 - CPU_TLB_ENTRY_BITS)
|
|
)
|
|
);
|
|
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
|
|
tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset));
|
|
tcg_out32 (s, (RLWINM
|
|
| RA (r2)
|
|
| RS (addr_reg)
|
|
| SH (0)
|
|
| MB ((32 - s_bits) & 31)
|
|
| ME (31 - TARGET_PAGE_BITS)
|
|
)
|
|
);
|
|
#else
|
|
tcg_out_rld (s, RLDICL, r0, addr_reg,
|
|
64 - TARGET_PAGE_BITS,
|
|
64 - CPU_TLB_BITS);
|
|
tcg_out_rld (s, RLDICR, r0, r0,
|
|
CPU_TLB_ENTRY_BITS,
|
|
63 - CPU_TLB_ENTRY_BITS);
|
|
|
|
tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
|
|
tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
|
|
|
|
if (!s_bits) {
|
|
tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
|
|
}
|
|
else {
|
|
tcg_out_rld (s, RLDICL, r2, addr_reg,
|
|
64 - TARGET_PAGE_BITS,
|
|
TARGET_PAGE_BITS - s_bits);
|
|
tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
|
|
}
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
|
|
{
|
|
int addr_reg, data_reg, r0, r1, rbase, mem_index, s_bits, bswap;
|
|
#ifdef CONFIG_SOFTMMU
|
|
int r2;
|
|
void *label1_ptr, *label2_ptr;
|
|
#endif
|
|
|
|
data_reg = *args++;
|
|
addr_reg = *args++;
|
|
mem_index = *args;
|
|
s_bits = opc & 3;
|
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
r0 = 3;
|
|
r1 = 4;
|
|
r2 = 0;
|
|
rbase = 0;
|
|
|
|
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
|
|
offsetof (CPUState, tlb_table[mem_index][0].addr_read));
|
|
|
|
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
|
|
|
|
label1_ptr = s->code_ptr;
|
|
#ifdef FAST_PATH
|
|
tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
|
|
#endif
|
|
|
|
/* slow path */
|
|
tcg_out_mov (s, 3, addr_reg);
|
|
tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
|
|
|
|
tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
|
|
|
|
switch (opc) {
|
|
case 0|4:
|
|
tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
|
|
break;
|
|
case 1|4:
|
|
tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
|
|
break;
|
|
case 2|4:
|
|
tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
|
|
break;
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
if (data_reg != 3)
|
|
tcg_out_mov (s, data_reg, 3);
|
|
break;
|
|
}
|
|
label2_ptr = s->code_ptr;
|
|
tcg_out32 (s, B);
|
|
|
|
/* label1: fast path */
|
|
#ifdef FAST_PATH
|
|
reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
|
|
#endif
|
|
|
|
/* r0 now contains &env->tlb_table[mem_index][index].addr_read */
|
|
tcg_out32 (s, (LD
|
|
| RT (r0)
|
|
| RA (r0)
|
|
| (offsetof (CPUTLBEntry, addend)
|
|
- offsetof (CPUTLBEntry, addr_read))
|
|
));
|
|
/* r0 = env->tlb_table[mem_index][index].addend */
|
|
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
|
|
/* r0 = env->tlb_table[mem_index][index].addend + addr */
|
|
|
|
#else /* !CONFIG_SOFTMMU */
|
|
#if TARGET_LONG_BITS == 32
|
|
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
|
|
#endif
|
|
r0 = addr_reg;
|
|
r1 = 3;
|
|
rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
|
|
#endif
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
bswap = 0;
|
|
#else
|
|
bswap = 1;
|
|
#endif
|
|
switch (opc) {
|
|
default:
|
|
case 0:
|
|
tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
|
|
break;
|
|
case 0|4:
|
|
tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
|
|
tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
|
|
break;
|
|
case 1:
|
|
if (bswap)
|
|
tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
|
|
else
|
|
tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
|
|
break;
|
|
case 1|4:
|
|
if (bswap) {
|
|
tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
|
|
tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
|
|
}
|
|
else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
|
|
break;
|
|
case 2:
|
|
if (bswap)
|
|
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
|
|
else
|
|
tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
|
|
break;
|
|
case 2|4:
|
|
if (bswap) {
|
|
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
|
|
tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
|
|
}
|
|
else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
|
|
break;
|
|
case 3:
|
|
#ifdef CONFIG_USE_GUEST_BASE
|
|
if (bswap) {
|
|
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
|
tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
|
|
tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1));
|
|
tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
|
|
}
|
|
else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
|
|
#else
|
|
if (bswap) {
|
|
tcg_out_movi32 (s, 0, 4);
|
|
tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
|
|
tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
|
|
tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
|
|
}
|
|
else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
|
|
#endif
|
|
break;
|
|
}
|
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
|
|
#endif
|
|
}
|
|
|
|
static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
|
|
{
|
|
int addr_reg, r0, r1, rbase, data_reg, mem_index, bswap;
|
|
#ifdef CONFIG_SOFTMMU
|
|
int r2;
|
|
void *label1_ptr, *label2_ptr;
|
|
#endif
|
|
|
|
data_reg = *args++;
|
|
addr_reg = *args++;
|
|
mem_index = *args;
|
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
r0 = 3;
|
|
r1 = 4;
|
|
r2 = 0;
|
|
rbase = 0;
|
|
|
|
tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
|
|
offsetof (CPUState, tlb_table[mem_index][0].addr_write));
|
|
|
|
tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
|
|
|
|
label1_ptr = s->code_ptr;
|
|
#ifdef FAST_PATH
|
|
tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
|
|
#endif
|
|
|
|
/* slow path */
|
|
tcg_out_mov (s, 3, addr_reg);
|
|
tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
|
|
tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
|
|
|
|
tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
|
|
|
|
label2_ptr = s->code_ptr;
|
|
tcg_out32 (s, B);
|
|
|
|
/* label1: fast path */
|
|
#ifdef FAST_PATH
|
|
reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
|
|
#endif
|
|
|
|
tcg_out32 (s, (LD
|
|
| RT (r0)
|
|
| RA (r0)
|
|
| (offsetof (CPUTLBEntry, addend)
|
|
- offsetof (CPUTLBEntry, addr_write))
|
|
));
|
|
/* r0 = env->tlb_table[mem_index][index].addend */
|
|
tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
|
|
/* r0 = env->tlb_table[mem_index][index].addend + addr */
|
|
|
|
#else /* !CONFIG_SOFTMMU */
|
|
#if TARGET_LONG_BITS == 32
|
|
tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
|
|
#endif
|
|
r1 = 3;
|
|
r0 = addr_reg;
|
|
rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
|
|
#endif
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
bswap = 0;
|
|
#else
|
|
bswap = 1;
|
|
#endif
|
|
switch (opc) {
|
|
case 0:
|
|
tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
|
|
break;
|
|
case 1:
|
|
if (bswap)
|
|
tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
|
|
else
|
|
tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
|
|
break;
|
|
case 2:
|
|
if (bswap)
|
|
tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
|
|
else
|
|
tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
|
|
break;
|
|
case 3:
|
|
if (bswap) {
|
|
tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
|
|
tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
|
|
tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
|
|
tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
|
|
}
|
|
else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
|
|
break;
|
|
}
|
|
|
|
#ifdef CONFIG_SOFTMMU
|
|
reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
|
|
#endif
|
|
}
|
|
|
|
void tcg_target_qemu_prologue (TCGContext *s)
|
|
{
|
|
int i, frame_size;
|
|
#ifndef __APPLE__
|
|
uint64_t addr;
|
|
#endif
|
|
|
|
frame_size = 0
|
|
+ 8 /* back chain */
|
|
+ 8 /* CR */
|
|
+ 8 /* LR */
|
|
+ 8 /* compiler doubleword */
|
|
+ 8 /* link editor doubleword */
|
|
+ 8 /* TOC save area */
|
|
+ TCG_STATIC_CALL_ARGS_SIZE
|
|
+ ARRAY_SIZE (tcg_target_callee_save_regs) * 8
|
|
;
|
|
frame_size = (frame_size + 15) & ~15;
|
|
|
|
#ifndef __APPLE__
|
|
/* First emit adhoc function descriptor */
|
|
addr = (uint64_t) s->code_ptr + 24;
|
|
tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
|
|
s->code_ptr += 16; /* skip TOC and environment pointer */
|
|
#endif
|
|
|
|
/* Prologue */
|
|
tcg_out32 (s, MFSPR | RT (0) | LR);
|
|
tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
|
|
for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
|
|
tcg_out32 (s, (STD
|
|
| RS (tcg_target_callee_save_regs[i])
|
|
| RA (1)
|
|
| (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
|
|
)
|
|
);
|
|
tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
|
|
|
|
#ifdef CONFIG_USE_GUEST_BASE
|
|
tcg_out_movi (s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
|
|
#endif
|
|
|
|
tcg_out32 (s, MTSPR | RS (3) | CTR);
|
|
tcg_out32 (s, BCCTR | BO_ALWAYS);
|
|
|
|
/* Epilogue */
|
|
tb_ret_addr = s->code_ptr;
|
|
|
|
for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
|
|
tcg_out32 (s, (LD
|
|
| RT (tcg_target_callee_save_regs[i])
|
|
| RA (1)
|
|
| (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
|
|
)
|
|
);
|
|
tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16));
|
|
tcg_out32 (s, MTSPR | RS (0) | LR);
|
|
tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
|
|
tcg_out32 (s, BCLR | BO_ALWAYS);
|
|
}
|
|
|
|
static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
|
|
tcg_target_long arg2)
|
|
{
|
|
if (type == TCG_TYPE_I32)
|
|
tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
|
|
else
|
|
tcg_out_ldsta (s, ret, arg1, arg2, LD, LDX);
|
|
}
|
|
|
|
static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
|
|
tcg_target_long arg2)
|
|
{
|
|
if (type == TCG_TYPE_I32)
|
|
tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
|
|
else
|
|
tcg_out_ldsta (s, arg, arg1, arg2, STD, STDX);
|
|
}
|
|
|
|
static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
|
|
{
|
|
if (!si && rt == ra)
|
|
return;
|
|
|
|
if (si == (int16_t) si)
|
|
tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
|
|
else {
|
|
uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
|
|
tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
|
|
tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
|
|
}
|
|
}
|
|
|
|
static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
|
|
{
|
|
/* XXX: suboptimal */
|
|
if (si == (int16_t) si
|
|
|| ((((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0))
|
|
ppc_addi32 (s, rt, ra, si);
|
|
else {
|
|
tcg_out_movi (s, TCG_TYPE_I64, 0, si);
|
|
tcg_out32 (s, ADD | RT (rt) | RA (ra));
|
|
}
|
|
}
|
|
|
|
static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val)
|
|
{
|
|
ppc_addi64 (s, reg, reg, val);
|
|
}
|
|
|
|
static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
|
|
int const_arg2, int cr, int arch64)
|
|
{
|
|
int imm;
|
|
uint32_t op;
|
|
|
|
switch (cond) {
|
|
case TCG_COND_EQ:
|
|
case TCG_COND_NE:
|
|
if (const_arg2) {
|
|
if ((int16_t) arg2 == arg2) {
|
|
op = CMPI;
|
|
imm = 1;
|
|
break;
|
|
}
|
|
else if ((uint16_t) arg2 == arg2) {
|
|
op = CMPLI;
|
|
imm = 1;
|
|
break;
|
|
}
|
|
}
|
|
op = CMPL;
|
|
imm = 0;
|
|
break;
|
|
|
|
case TCG_COND_LT:
|
|
case TCG_COND_GE:
|
|
case TCG_COND_LE:
|
|
case TCG_COND_GT:
|
|
if (const_arg2) {
|
|
if ((int16_t) arg2 == arg2) {
|
|
op = CMPI;
|
|
imm = 1;
|
|
break;
|
|
}
|
|
}
|
|
op = CMP;
|
|
imm = 0;
|
|
break;
|
|
|
|
case TCG_COND_LTU:
|
|
case TCG_COND_GEU:
|
|
case TCG_COND_LEU:
|
|
case TCG_COND_GTU:
|
|
if (const_arg2) {
|
|
if ((uint16_t) arg2 == arg2) {
|
|
op = CMPLI;
|
|
imm = 1;
|
|
break;
|
|
}
|
|
}
|
|
op = CMPL;
|
|
imm = 0;
|
|
break;
|
|
|
|
default:
|
|
tcg_abort ();
|
|
}
|
|
op |= BF (cr) | (arch64 << 21);
|
|
|
|
if (imm)
|
|
tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
|
|
else {
|
|
if (const_arg2) {
|
|
tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
|
|
tcg_out32 (s, op | RA (arg1) | RB (0));
|
|
}
|
|
else
|
|
tcg_out32 (s, op | RA (arg1) | RB (arg2));
|
|
}
|
|
|
|
}
|
|
|
|
static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond,
|
|
TCGArg arg0, TCGArg arg1, TCGArg arg2,
|
|
int const_arg2)
|
|
{
|
|
int crop, sh, arg;
|
|
|
|
switch (cond) {
|
|
case TCG_COND_EQ:
|
|
if (const_arg2) {
|
|
if (!arg2) {
|
|
arg = arg1;
|
|
}
|
|
else {
|
|
arg = 0;
|
|
if ((uint16_t) arg2 == arg2) {
|
|
tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
|
|
}
|
|
else {
|
|
tcg_out_movi (s, type, 0, arg2);
|
|
tcg_out32 (s, XOR | SAB (arg1, 0, 0));
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
arg = 0;
|
|
tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
|
|
}
|
|
|
|
if (type == TCG_TYPE_I64) {
|
|
tcg_out32 (s, CNTLZD | RS (arg) | RA (0));
|
|
tcg_out_rld (s, RLDICL, arg0, 0, 58, 6);
|
|
}
|
|
else {
|
|
tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
|
|
tcg_out32 (s, (RLWINM
|
|
| RA (arg0)
|
|
| RS (0)
|
|
| SH (27)
|
|
| MB (5)
|
|
| ME (31)
|
|
)
|
|
);
|
|
}
|
|
break;
|
|
|
|
case TCG_COND_NE:
|
|
if (const_arg2) {
|
|
if (!arg2) {
|
|
arg = arg1;
|
|
}
|
|
else {
|
|
arg = 0;
|
|
if ((uint16_t) arg2 == arg2) {
|
|
tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
|
|
}
|
|
else {
|
|
tcg_out_movi (s, type, 0, arg2);
|
|
tcg_out32 (s, XOR | SAB (arg1, 0, 0));
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
arg = 0;
|
|
tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
|
|
}
|
|
|
|
if (arg == arg1 && arg1 == arg0) {
|
|
tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
|
|
tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
|
|
}
|
|
else {
|
|
tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
|
|
tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
|
|
}
|
|
break;
|
|
|
|
case TCG_COND_GT:
|
|
case TCG_COND_GTU:
|
|
sh = 30;
|
|
crop = 0;
|
|
goto crtest;
|
|
|
|
case TCG_COND_LT:
|
|
case TCG_COND_LTU:
|
|
sh = 29;
|
|
crop = 0;
|
|
goto crtest;
|
|
|
|
case TCG_COND_GE:
|
|
case TCG_COND_GEU:
|
|
sh = 31;
|
|
crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
|
|
goto crtest;
|
|
|
|
case TCG_COND_LE:
|
|
case TCG_COND_LEU:
|
|
sh = 31;
|
|
crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
|
|
crtest:
|
|
tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type == TCG_TYPE_I64);
|
|
if (crop) tcg_out32 (s, crop);
|
|
tcg_out32 (s, MFCR | RT (0));
|
|
tcg_out32 (s, (RLWINM
|
|
| RA (arg0)
|
|
| RS (0)
|
|
| SH (sh)
|
|
| MB (31)
|
|
| ME (31)
|
|
)
|
|
);
|
|
break;
|
|
|
|
default:
|
|
tcg_abort ();
|
|
}
|
|
}
|
|
|
|
static void tcg_out_bc (TCGContext *s, int bc, int label_index)
|
|
{
|
|
TCGLabel *l = &s->labels[label_index];
|
|
|
|
if (l->has_value)
|
|
tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
|
|
else {
|
|
uint16_t val = *(uint16_t *) &s->code_ptr[2];
|
|
|
|
/* Thanks to Andrzej Zaborowski */
|
|
tcg_out32 (s, bc | (val & 0xfffc));
|
|
tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
|
|
}
|
|
}
|
|
|
|
static void tcg_out_brcond (TCGContext *s, TCGCond cond,
|
|
TCGArg arg1, TCGArg arg2, int const_arg2,
|
|
int label_index, int arch64)
|
|
{
|
|
tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
|
|
tcg_out_bc (s, tcg_to_bc[cond], label_index);
|
|
}
|
|
|
|
void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
|
|
{
|
|
TCGContext s;
|
|
unsigned long patch_size;
|
|
|
|
s.code_ptr = (uint8_t *) jmp_addr;
|
|
tcg_out_b (&s, 0, addr);
|
|
patch_size = s.code_ptr - (uint8_t *) jmp_addr;
|
|
flush_icache_range (jmp_addr, jmp_addr + patch_size);
|
|
}
|
|
|
|
static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
|
|
const int *const_args)
|
|
{
|
|
int c;
|
|
|
|
switch (opc) {
|
|
case INDEX_op_exit_tb:
|
|
tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
|
|
tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
|
|
break;
|
|
case INDEX_op_goto_tb:
|
|
if (s->tb_jmp_offset) {
|
|
/* direct jump method */
|
|
|
|
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
|
s->code_ptr += 28;
|
|
}
|
|
else {
|
|
tcg_abort ();
|
|
}
|
|
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
|
break;
|
|
case INDEX_op_br:
|
|
{
|
|
TCGLabel *l = &s->labels[args[0]];
|
|
|
|
if (l->has_value) {
|
|
tcg_out_b (s, 0, l->u.value);
|
|
}
|
|
else {
|
|
uint32_t val = *(uint32_t *) s->code_ptr;
|
|
|
|
/* Thanks to Andrzej Zaborowski */
|
|
tcg_out32 (s, B | (val & 0x3fffffc));
|
|
tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
|
|
}
|
|
}
|
|
break;
|
|
case INDEX_op_call:
|
|
tcg_out_call (s, args[0], const_args[0]);
|
|
break;
|
|
case INDEX_op_jmp:
|
|
if (const_args[0]) {
|
|
tcg_out_b (s, 0, args[0]);
|
|
}
|
|
else {
|
|
tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
|
|
tcg_out32 (s, BCCTR | BO_ALWAYS);
|
|
}
|
|
break;
|
|
case INDEX_op_movi_i32:
|
|
tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
|
|
break;
|
|
case INDEX_op_movi_i64:
|
|
tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
|
|
break;
|
|
case INDEX_op_ld8u_i32:
|
|
case INDEX_op_ld8u_i64:
|
|
tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
|
|
break;
|
|
case INDEX_op_ld8s_i32:
|
|
case INDEX_op_ld8s_i64:
|
|
tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
|
|
tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
|
|
break;
|
|
case INDEX_op_ld16u_i32:
|
|
case INDEX_op_ld16u_i64:
|
|
tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
|
|
break;
|
|
case INDEX_op_ld16s_i32:
|
|
case INDEX_op_ld16s_i64:
|
|
tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
|
|
break;
|
|
case INDEX_op_ld_i32:
|
|
case INDEX_op_ld32u_i64:
|
|
tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
|
|
break;
|
|
case INDEX_op_ld32s_i64:
|
|
tcg_out_ldsta (s, args[0], args[1], args[2], LWA, LWAX);
|
|
break;
|
|
case INDEX_op_ld_i64:
|
|
tcg_out_ldsta (s, args[0], args[1], args[2], LD, LDX);
|
|
break;
|
|
case INDEX_op_st8_i32:
|
|
case INDEX_op_st8_i64:
|
|
tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
|
|
break;
|
|
case INDEX_op_st16_i32:
|
|
case INDEX_op_st16_i64:
|
|
tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
|
|
break;
|
|
case INDEX_op_st_i32:
|
|
case INDEX_op_st32_i64:
|
|
tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
|
|
break;
|
|
case INDEX_op_st_i64:
|
|
tcg_out_ldsta (s, args[0], args[1], args[2], STD, STDX);
|
|
break;
|
|
|
|
case INDEX_op_add_i32:
|
|
if (const_args[2])
|
|
ppc_addi32 (s, args[0], args[1], args[2]);
|
|
else
|
|
tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
|
|
break;
|
|
case INDEX_op_sub_i32:
|
|
if (const_args[2])
|
|
ppc_addi32 (s, args[0], args[1], -args[2]);
|
|
else
|
|
tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
|
|
break;
|
|
|
|
case INDEX_op_and_i64:
|
|
case INDEX_op_and_i32:
|
|
if (const_args[2]) {
|
|
if ((args[2] & 0xffff) == args[2])
|
|
tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
|
|
else if ((args[2] & 0xffff0000) == args[2])
|
|
tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
|
|
| ((args[2] >> 16) & 0xffff));
|
|
else {
|
|
tcg_out_movi (s, (opc == INDEX_op_and_i32
|
|
? TCG_TYPE_I32
|
|
: TCG_TYPE_I64),
|
|
0, args[2]);
|
|
tcg_out32 (s, AND | SAB (args[1], args[0], 0));
|
|
}
|
|
}
|
|
else
|
|
tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
case INDEX_op_or_i64:
|
|
case INDEX_op_or_i32:
|
|
if (const_args[2]) {
|
|
if (args[2] & 0xffff) {
|
|
tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
|
|
| (args[2] & 0xffff));
|
|
if (args[2] >> 16)
|
|
tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
|
|
| ((args[2] >> 16) & 0xffff));
|
|
}
|
|
else {
|
|
tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
|
|
| ((args[2] >> 16) & 0xffff));
|
|
}
|
|
}
|
|
else
|
|
tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
case INDEX_op_xor_i64:
|
|
case INDEX_op_xor_i32:
|
|
if (const_args[2]) {
|
|
if ((args[2] & 0xffff) == args[2])
|
|
tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
|
|
| (args[2] & 0xffff));
|
|
else if ((args[2] & 0xffff0000) == args[2])
|
|
tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
|
|
| ((args[2] >> 16) & 0xffff));
|
|
else {
|
|
tcg_out_movi (s, (opc == INDEX_op_and_i32
|
|
? TCG_TYPE_I32
|
|
: TCG_TYPE_I64),
|
|
0, args[2]);
|
|
tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
|
|
}
|
|
}
|
|
else
|
|
tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
|
|
case INDEX_op_mul_i32:
|
|
if (const_args[2]) {
|
|
if (args[2] == (int16_t) args[2])
|
|
tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
|
|
| (args[2] & 0xffff));
|
|
else {
|
|
tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
|
|
tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
|
|
}
|
|
}
|
|
else
|
|
tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
|
|
break;
|
|
|
|
case INDEX_op_div_i32:
|
|
tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
|
|
break;
|
|
|
|
case INDEX_op_divu_i32:
|
|
tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
|
|
break;
|
|
|
|
case INDEX_op_rem_i32:
|
|
tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
|
|
tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
|
|
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
|
|
break;
|
|
|
|
case INDEX_op_remu_i32:
|
|
tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
|
|
tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
|
|
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
|
|
break;
|
|
|
|
case INDEX_op_shl_i32:
|
|
if (const_args[2]) {
|
|
tcg_out32 (s, (RLWINM
|
|
| RA (args[0])
|
|
| RS (args[1])
|
|
| SH (args[2])
|
|
| MB (0)
|
|
| ME (31 - args[2])
|
|
)
|
|
);
|
|
}
|
|
else
|
|
tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
case INDEX_op_shr_i32:
|
|
if (const_args[2]) {
|
|
tcg_out32 (s, (RLWINM
|
|
| RA (args[0])
|
|
| RS (args[1])
|
|
| SH (32 - args[2])
|
|
| MB (args[2])
|
|
| ME (31)
|
|
)
|
|
);
|
|
}
|
|
else
|
|
tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
case INDEX_op_sar_i32:
|
|
if (const_args[2])
|
|
tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
|
|
else
|
|
tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
|
|
case INDEX_op_brcond_i32:
|
|
tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
|
|
break;
|
|
|
|
case INDEX_op_brcond_i64:
|
|
tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
|
|
break;
|
|
|
|
case INDEX_op_neg_i32:
|
|
case INDEX_op_neg_i64:
|
|
tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
|
|
break;
|
|
|
|
case INDEX_op_add_i64:
|
|
if (const_args[2])
|
|
ppc_addi64 (s, args[0], args[1], args[2]);
|
|
else
|
|
tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
|
|
break;
|
|
case INDEX_op_sub_i64:
|
|
if (const_args[2])
|
|
ppc_addi64 (s, args[0], args[1], -args[2]);
|
|
else
|
|
tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
|
|
break;
|
|
|
|
case INDEX_op_shl_i64:
|
|
if (const_args[2])
|
|
tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]);
|
|
else
|
|
tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
case INDEX_op_shr_i64:
|
|
if (const_args[2])
|
|
tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]);
|
|
else
|
|
tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
case INDEX_op_sar_i64:
|
|
if (const_args[2]) {
|
|
int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
|
|
tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
|
|
}
|
|
else
|
|
tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
|
|
break;
|
|
|
|
case INDEX_op_mul_i64:
|
|
tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
|
|
break;
|
|
case INDEX_op_div_i64:
|
|
tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
|
|
break;
|
|
case INDEX_op_divu_i64:
|
|
tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
|
|
break;
|
|
case INDEX_op_rem_i64:
|
|
tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
|
|
tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
|
|
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
|
|
break;
|
|
case INDEX_op_remu_i64:
|
|
tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
|
|
tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
|
|
tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
|
|
break;
|
|
|
|
case INDEX_op_qemu_ld8u:
|
|
tcg_out_qemu_ld (s, args, 0);
|
|
break;
|
|
case INDEX_op_qemu_ld8s:
|
|
tcg_out_qemu_ld (s, args, 0 | 4);
|
|
break;
|
|
case INDEX_op_qemu_ld16u:
|
|
tcg_out_qemu_ld (s, args, 1);
|
|
break;
|
|
case INDEX_op_qemu_ld16s:
|
|
tcg_out_qemu_ld (s, args, 1 | 4);
|
|
break;
|
|
case INDEX_op_qemu_ld32:
|
|
case INDEX_op_qemu_ld32u:
|
|
tcg_out_qemu_ld (s, args, 2);
|
|
break;
|
|
case INDEX_op_qemu_ld32s:
|
|
tcg_out_qemu_ld (s, args, 2 | 4);
|
|
break;
|
|
case INDEX_op_qemu_ld64:
|
|
tcg_out_qemu_ld (s, args, 3);
|
|
break;
|
|
case INDEX_op_qemu_st8:
|
|
tcg_out_qemu_st (s, args, 0);
|
|
break;
|
|
case INDEX_op_qemu_st16:
|
|
tcg_out_qemu_st (s, args, 1);
|
|
break;
|
|
case INDEX_op_qemu_st32:
|
|
tcg_out_qemu_st (s, args, 2);
|
|
break;
|
|
case INDEX_op_qemu_st64:
|
|
tcg_out_qemu_st (s, args, 3);
|
|
break;
|
|
|
|
case INDEX_op_ext8s_i32:
|
|
case INDEX_op_ext8s_i64:
|
|
c = EXTSB;
|
|
goto gen_ext;
|
|
case INDEX_op_ext16s_i32:
|
|
case INDEX_op_ext16s_i64:
|
|
c = EXTSH;
|
|
goto gen_ext;
|
|
case INDEX_op_ext32s_i64:
|
|
c = EXTSW;
|
|
goto gen_ext;
|
|
gen_ext:
|
|
tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
|
|
break;
|
|
|
|
case INDEX_op_setcond_i32:
|
|
tcg_out_setcond (s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
|
|
const_args[2]);
|
|
break;
|
|
case INDEX_op_setcond_i64:
|
|
tcg_out_setcond (s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
|
|
const_args[2]);
|
|
break;
|
|
|
|
default:
|
|
tcg_dump_ops (s, stderr);
|
|
tcg_abort ();
|
|
}
|
|
}
|
|
|
|
static const TCGTargetOpDef ppc_op_defs[] = {
|
|
{ INDEX_op_exit_tb, { } },
|
|
{ INDEX_op_goto_tb, { } },
|
|
{ INDEX_op_call, { "ri" } },
|
|
{ INDEX_op_jmp, { "ri" } },
|
|
{ INDEX_op_br, { } },
|
|
|
|
{ INDEX_op_mov_i32, { "r", "r" } },
|
|
{ INDEX_op_mov_i64, { "r", "r" } },
|
|
{ INDEX_op_movi_i32, { "r" } },
|
|
{ INDEX_op_movi_i64, { "r" } },
|
|
|
|
{ INDEX_op_ld8u_i32, { "r", "r" } },
|
|
{ INDEX_op_ld8s_i32, { "r", "r" } },
|
|
{ INDEX_op_ld16u_i32, { "r", "r" } },
|
|
{ INDEX_op_ld16s_i32, { "r", "r" } },
|
|
{ INDEX_op_ld_i32, { "r", "r" } },
|
|
{ INDEX_op_ld_i64, { "r", "r" } },
|
|
{ INDEX_op_st8_i32, { "r", "r" } },
|
|
{ INDEX_op_st8_i64, { "r", "r" } },
|
|
{ INDEX_op_st16_i32, { "r", "r" } },
|
|
{ INDEX_op_st16_i64, { "r", "r" } },
|
|
{ INDEX_op_st_i32, { "r", "r" } },
|
|
{ INDEX_op_st_i64, { "r", "r" } },
|
|
{ INDEX_op_st32_i64, { "r", "r" } },
|
|
|
|
{ INDEX_op_ld8u_i64, { "r", "r" } },
|
|
{ INDEX_op_ld8s_i64, { "r", "r" } },
|
|
{ INDEX_op_ld16u_i64, { "r", "r" } },
|
|
{ INDEX_op_ld16s_i64, { "r", "r" } },
|
|
{ INDEX_op_ld32u_i64, { "r", "r" } },
|
|
{ INDEX_op_ld32s_i64, { "r", "r" } },
|
|
{ INDEX_op_ld_i64, { "r", "r" } },
|
|
|
|
{ INDEX_op_add_i32, { "r", "r", "ri" } },
|
|
{ INDEX_op_mul_i32, { "r", "r", "ri" } },
|
|
{ INDEX_op_div_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_divu_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_rem_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_remu_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_sub_i32, { "r", "r", "ri" } },
|
|
{ INDEX_op_and_i32, { "r", "r", "ri" } },
|
|
{ INDEX_op_or_i32, { "r", "r", "ri" } },
|
|
{ INDEX_op_xor_i32, { "r", "r", "ri" } },
|
|
|
|
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
|
|
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
|
|
{ INDEX_op_sar_i32, { "r", "r", "ri" } },
|
|
|
|
{ INDEX_op_brcond_i32, { "r", "ri" } },
|
|
{ INDEX_op_brcond_i64, { "r", "ri" } },
|
|
|
|
{ INDEX_op_neg_i32, { "r", "r" } },
|
|
|
|
{ INDEX_op_add_i64, { "r", "r", "ri" } },
|
|
{ INDEX_op_sub_i64, { "r", "r", "ri" } },
|
|
{ INDEX_op_and_i64, { "r", "r", "rZ" } },
|
|
{ INDEX_op_or_i64, { "r", "r", "rZ" } },
|
|
{ INDEX_op_xor_i64, { "r", "r", "rZ" } },
|
|
|
|
{ INDEX_op_shl_i64, { "r", "r", "ri" } },
|
|
{ INDEX_op_shr_i64, { "r", "r", "ri" } },
|
|
{ INDEX_op_sar_i64, { "r", "r", "ri" } },
|
|
|
|
{ INDEX_op_mul_i64, { "r", "r", "r" } },
|
|
{ INDEX_op_div_i64, { "r", "r", "r" } },
|
|
{ INDEX_op_divu_i64, { "r", "r", "r" } },
|
|
{ INDEX_op_rem_i64, { "r", "r", "r" } },
|
|
{ INDEX_op_remu_i64, { "r", "r", "r" } },
|
|
|
|
{ INDEX_op_neg_i64, { "r", "r" } },
|
|
|
|
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld16u, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld16s, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld32, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld32u, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld32s, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld64, { "r", "L" } },
|
|
|
|
{ INDEX_op_qemu_st8, { "S", "S" } },
|
|
{ INDEX_op_qemu_st16, { "S", "S" } },
|
|
{ INDEX_op_qemu_st32, { "S", "S" } },
|
|
{ INDEX_op_qemu_st64, { "S", "S" } },
|
|
|
|
{ INDEX_op_ext8s_i32, { "r", "r" } },
|
|
{ INDEX_op_ext16s_i32, { "r", "r" } },
|
|
{ INDEX_op_ext8s_i64, { "r", "r" } },
|
|
{ INDEX_op_ext16s_i64, { "r", "r" } },
|
|
{ INDEX_op_ext32s_i64, { "r", "r" } },
|
|
|
|
{ INDEX_op_setcond_i32, { "r", "r", "ri" } },
|
|
{ INDEX_op_setcond_i64, { "r", "r", "ri" } },
|
|
|
|
{ -1 },
|
|
};
|
|
|
|
void tcg_target_init (TCGContext *s)
|
|
{
|
|
tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
|
|
tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
|
|
tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
|
|
(1 << TCG_REG_R0) |
|
|
#ifdef __APPLE__
|
|
(1 << TCG_REG_R2) |
|
|
#endif
|
|
(1 << TCG_REG_R3) |
|
|
(1 << TCG_REG_R4) |
|
|
(1 << TCG_REG_R5) |
|
|
(1 << TCG_REG_R6) |
|
|
(1 << TCG_REG_R7) |
|
|
(1 << TCG_REG_R8) |
|
|
(1 << TCG_REG_R9) |
|
|
(1 << TCG_REG_R10) |
|
|
(1 << TCG_REG_R11) |
|
|
(1 << TCG_REG_R12)
|
|
);
|
|
|
|
tcg_regset_clear (s->reserved_regs);
|
|
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
|
|
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
|
|
#ifndef __APPLE__
|
|
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
|
|
#endif
|
|
tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
|
|
|
|
#ifdef CONFIG_USE_GUEST_BASE
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
|
|
#endif
|
|
|
|
tcg_add_target_add_op_defs (ppc_op_defs);
|
|
}
|