3f9f76d5bb
This commit attempts to fix a technical hiccup first mentioned by Richard Henderson in https://lists.nongnu.org/archive/html/qemu-devel/2021-05/msg06247.html To sumarize the hiccup here, when radix-style mmus are translating an address, they might need to call a second level of translation, with hypervisor privileges. However, the way it was being done up until this point meant that the second level translation had the same privileges as the first level. It could lead to a bug in address translation when running KVM inside a TCG guest, but this bug was never experienced by users, so this isn't as much a bug fix as it is a correctness cleanup. This patch attempts that cleanup by making radix64_*_xlate functions receive the mmu_idx, and passing one with the correct permission for the second level translation. The mmuidx macros added by this patch are only correct for non-bookE mmus, because BookE style set the IS and DS bits inverted and there might be other subtle differences. However, there doesn't seem to be BookE cpus that have radix-style mmus, so we left a comment there to document the issue, in case a machine does have that and was missed. As part of this cleanup, we now need to send the correct mmmu_idx when calling get_phys_page_debug, otherwise we might not be able to see the memory that the CPU could Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210628133610.1143-2-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
74 lines
2.7 KiB
C
74 lines
2.7 KiB
C
#ifndef MMU_RADIX64_H
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#define MMU_RADIX64_H
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#ifndef CONFIG_USER_ONLY
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/* Radix Quadrants */
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#define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF
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#define R_EADDR_QUADRANT 0xC000000000000000
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#define R_EADDR_QUADRANT0 0x0000000000000000
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#define R_EADDR_QUADRANT1 0x4000000000000000
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#define R_EADDR_QUADRANT2 0x8000000000000000
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#define R_EADDR_QUADRANT3 0xC000000000000000
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/* Radix Partition Table Entry Fields */
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#define PATE1_R_PRTB 0x0FFFFFFFFFFFF000
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#define PATE1_R_PRTS 0x000000000000001F
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/* Radix Process Table Entry Fields */
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#define PRTBE_R_GET_RTS(rts) \
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((((rts >> 58) & 0x18) | ((rts >> 5) & 0x7)) + 31)
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#define PRTBE_R_RPDB 0x0FFFFFFFFFFFFF00
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#define PRTBE_R_RPDS 0x000000000000001F
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/* Radix Page Directory/Table Entry Fields */
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#define R_PTE_VALID 0x8000000000000000
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#define R_PTE_LEAF 0x4000000000000000
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#define R_PTE_SW0 0x2000000000000000
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#define R_PTE_RPN 0x01FFFFFFFFFFF000
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#define R_PTE_SW1 0x0000000000000E00
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#define R_GET_SW(sw) (((sw >> 58) & 0x8) | ((sw >> 9) & 0x7))
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#define R_PTE_R 0x0000000000000100
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#define R_PTE_C 0x0000000000000080
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#define R_PTE_ATT 0x0000000000000030
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#define R_PTE_ATT_NORMAL 0x0000000000000000
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#define R_PTE_ATT_SAO 0x0000000000000010
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#define R_PTE_ATT_NI_IO 0x0000000000000020
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#define R_PTE_ATT_TOLERANT_IO 0x0000000000000030
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#define R_PTE_EAA_PRIV 0x0000000000000008
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#define R_PTE_EAA_R 0x0000000000000004
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#define R_PTE_EAA_RW 0x0000000000000002
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#define R_PTE_EAA_X 0x0000000000000001
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#define R_PDE_NLB PRTBE_R_RPDB
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#define R_PDE_NLS PRTBE_R_RPDS
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#ifdef TARGET_PPC64
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bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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hwaddr *raddr, int *psizep, int *protp, int mmu_idx,
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bool guest_visible);
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static inline int ppc_radix64_get_prot_eaa(uint64_t pte)
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{
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return (pte & R_PTE_EAA_R ? PAGE_READ : 0) |
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(pte & R_PTE_EAA_RW ? PAGE_READ | PAGE_WRITE : 0) |
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(pte & R_PTE_EAA_X ? PAGE_EXEC : 0);
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}
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static inline int ppc_radix64_get_prot_amr(const PowerPCCPU *cpu)
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{
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const CPUPPCState *env = &cpu->env;
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int amr = env->spr[SPR_AMR] >> 62; /* We only care about key0 AMR63:62 */
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int iamr = env->spr[SPR_IAMR] >> 62; /* We only care about key0 IAMR63:62 */
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return (amr & 0x2 ? 0 : PAGE_WRITE) | /* Access denied if bit is set */
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(amr & 0x1 ? 0 : PAGE_READ) |
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(iamr & 0x1 ? 0 : PAGE_EXEC);
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}
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#endif /* TARGET_PPC64 */
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#endif /* CONFIG_USER_ONLY */
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#endif /* MMU_RADIX64_H */
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