350929172b
Coverity (CID1390589, CID1390608). Array size is RDMA_BAR1_REGS_SIZE, let's make sure the given address is in range. While there also: 1. Adjust the size of this bar to reasonable size 2. Report the size of the array with sizeof(array) Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180430200223.4119-6-marcel.apfelbaum@gmail.com>
123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
/*
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* QEMU VMWARE paravirtual RDMA device definitions
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef PVRDMA_PVRDMA_H
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#define PVRDMA_PVRDMA_H
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#include "hw/pci/pci.h"
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#include "hw/pci/msix.h"
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#include "../rdma_backend_defs.h"
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#include "../rdma_rm_defs.h"
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#include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h"
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#include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h"
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#include "pvrdma_dev_ring.h"
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/* BARs */
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#define RDMA_MSIX_BAR_IDX 0
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#define RDMA_REG_BAR_IDX 1
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#define RDMA_UAR_BAR_IDX 2
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#define RDMA_BAR0_MSIX_SIZE (16 * 1024)
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#define RDMA_BAR1_REGS_SIZE 64
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#define RDMA_BAR2_UAR_SIZE (0x1000 * MAX_UCS) /* each uc gets page */
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/* MSIX */
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#define RDMA_MAX_INTRS 3
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#define RDMA_MSIX_TABLE 0x0000
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#define RDMA_MSIX_PBA 0x2000
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/* Interrupts Vectors */
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#define INTR_VEC_CMD_RING 0
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#define INTR_VEC_CMD_ASYNC_EVENTS 1
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#define INTR_VEC_CMD_COMPLETION_Q 2
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/* HW attributes */
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#define PVRDMA_HW_NAME "pvrdma"
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#define PVRDMA_HW_VERSION 17
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#define PVRDMA_FW_VERSION 14
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typedef struct DSRInfo {
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dma_addr_t dma;
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struct pvrdma_device_shared_region *dsr;
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union pvrdma_cmd_req *req;
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union pvrdma_cmd_resp *rsp;
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struct pvrdma_ring *async_ring_state;
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PvrdmaRing async;
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struct pvrdma_ring *cq_ring_state;
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PvrdmaRing cq;
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} DSRInfo;
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typedef struct PVRDMADev {
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PCIDevice parent_obj;
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MemoryRegion msix;
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MemoryRegion regs;
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uint32_t regs_data[RDMA_BAR1_REGS_SIZE];
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MemoryRegion uar;
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uint32_t uar_data[RDMA_BAR2_UAR_SIZE];
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DSRInfo dsr_info;
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int interrupt_mask;
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struct ibv_device_attr dev_attr;
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uint64_t node_guid;
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char *backend_device_name;
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uint8_t backend_gid_idx;
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uint8_t backend_port_num;
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RdmaBackendDev backend_dev;
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RdmaDeviceResources rdma_dev_res;
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} PVRDMADev;
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#define PVRDMA_DEV(dev) OBJECT_CHECK(PVRDMADev, (dev), PVRDMA_HW_NAME)
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static inline int get_reg_val(PVRDMADev *dev, hwaddr addr, uint32_t *val)
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{
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int idx = addr >> 2;
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if (idx >= RDMA_BAR1_REGS_SIZE) {
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return -EINVAL;
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}
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*val = dev->regs_data[idx];
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return 0;
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}
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static inline int set_reg_val(PVRDMADev *dev, hwaddr addr, uint32_t val)
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{
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int idx = addr >> 2;
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if (idx >= RDMA_BAR1_REGS_SIZE) {
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return -EINVAL;
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}
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dev->regs_data[idx] = val;
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return 0;
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}
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static inline void post_interrupt(PVRDMADev *dev, unsigned vector)
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{
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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if (likely(!dev->interrupt_mask)) {
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msix_notify(pci_dev, vector);
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}
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}
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int execute_command(PVRDMADev *dev);
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#endif
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