3475187dd8
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1462 c046a42c-6fe2-441c-8c8c-71466251a162
1216 lines
39 KiB
C
1216 lines
39 KiB
C
/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h"
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#include "exec.h"
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#include "disas.h"
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#if !defined(CONFIG_SOFTMMU)
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h>
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#include <sys/ucontext.h>
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#endif
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int tb_invalidated_flag;
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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#if defined(TARGET_ARM) || defined(TARGET_SPARC)
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/* XXX: unify with i386 target */
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void cpu_loop_exit(void)
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{
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longjmp(env->jmp_env, 1);
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}
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#endif
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#ifndef TARGET_SPARC
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#define reg_T2
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#endif
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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void cpu_resume_from_signal(CPUState *env1, void *puc)
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{
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#if !defined(CONFIG_SOFTMMU)
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struct ucontext *uc = puc;
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#endif
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env = env1;
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/* XXX: restore cpu registers saved in host registers */
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#if !defined(CONFIG_SOFTMMU)
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if (puc) {
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/* XXX: use siglongjmp ? */
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sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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}
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#endif
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longjmp(env->jmp_env, 1);
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}
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/* main execution loop */
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int cpu_exec(CPUState *env1)
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{
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int saved_T0, saved_T1;
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#if defined(reg_T2)
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int saved_T2;
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#endif
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CPUState *saved_env;
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#if defined(TARGET_I386)
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#ifdef reg_EAX
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int saved_EAX;
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#endif
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#ifdef reg_ECX
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int saved_ECX;
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#endif
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#ifdef reg_EDX
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int saved_EDX;
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#endif
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#ifdef reg_EBX
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int saved_EBX;
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#endif
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#ifdef reg_ESP
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int saved_ESP;
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#endif
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#ifdef reg_EBP
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int saved_EBP;
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#endif
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#ifdef reg_ESI
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int saved_ESI;
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#endif
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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#elif defined(TARGET_SPARC)
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#if defined(reg_REGWPTR)
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uint32_t *saved_regwptr;
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#endif
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#endif
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#ifdef __sparc__
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int saved_i7, tmp_T0;
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#endif
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int code_gen_size, ret, interrupt_request;
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void (*gen_func)(void);
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TranslationBlock *tb, **ptb;
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target_ulong cs_base, pc;
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uint8_t *tc_ptr;
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unsigned int flags;
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/* first we save global registers */
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saved_env = env;
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env = env1;
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saved_T0 = T0;
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saved_T1 = T1;
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#if defined(reg_T2)
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saved_T2 = T2;
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#endif
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#ifdef __sparc__
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/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
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#endif
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#if defined(TARGET_I386)
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#ifdef reg_EAX
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saved_EAX = EAX;
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#endif
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#ifdef reg_ECX
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saved_ECX = ECX;
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#endif
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#ifdef reg_EDX
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saved_EDX = EDX;
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#endif
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#ifdef reg_EBX
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saved_EBX = EBX;
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#endif
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#ifdef reg_ESP
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saved_ESP = ESP;
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#endif
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#ifdef reg_EBP
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saved_EBP = EBP;
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#endif
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#ifdef reg_ESI
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saved_ESI = ESI;
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#endif
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#ifdef reg_EDI
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saved_EDI = EDI;
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#endif
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env_to_regs();
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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DF = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_ARM)
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{
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unsigned int psr;
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psr = env->cpsr;
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env->CF = (psr >> 29) & 1;
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env->NZF = (psr & 0xc0000000) ^ 0x40000000;
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env->VF = (psr << 3) & 0x80000000;
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env->QF = (psr >> 27) & 1;
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env->cpsr = psr & ~CACHED_CPSR_BITS;
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}
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#elif defined(TARGET_SPARC)
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#if defined(reg_REGWPTR)
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saved_regwptr = REGWPTR;
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#endif
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#elif defined(TARGET_PPC)
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#else
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#error unsupported target CPU
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#endif
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env->exception_index = -1;
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/* prepare setjmp context for exception handling */
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for(;;) {
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if (setjmp(env->jmp_env) == 0) {
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env->current_tb = NULL;
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/* if an exception is pending, we execute it here */
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if (env->exception_index >= 0) {
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if (env->exception_index >= EXCP_INTERRUPT) {
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/* exit request from the cpu execution loop */
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ret = env->exception_index;
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break;
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} else if (env->user_mode_only) {
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/* if user mode only, we simulate a fake exception
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which will be hanlded outside the cpu execution
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loop */
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#if defined(TARGET_I386)
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do_interrupt_user(env->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip);
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#endif
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ret = env->exception_index;
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break;
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} else {
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#if defined(TARGET_I386)
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/* simulate a real cpu exception. On i386, it can
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trigger new exceptions, but we do not handle
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double or triple faults yet. */
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do_interrupt(env->exception_index,
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env->exception_is_int,
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env->error_code,
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env->exception_next_eip, 0);
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#elif defined(TARGET_PPC)
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do_interrupt(env);
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#elif defined(TARGET_SPARC)
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do_interrupt(env->exception_index);
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#endif
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}
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env->exception_index = -1;
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}
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#ifdef USE_KQEMU
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if (kqemu_is_ok(env) && env->interrupt_request == 0) {
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int ret;
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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ret = kqemu_cpu_exec(env);
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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DF = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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if (ret == 1) {
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/* exception */
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longjmp(env->jmp_env, 1);
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} else if (ret == 2) {
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/* softmmu execution needed */
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} else {
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if (env->interrupt_request != 0) {
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/* hardware interrupt will be executed just after */
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} else {
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/* otherwise, we restart */
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longjmp(env->jmp_env, 1);
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}
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}
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}
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#endif
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T0 = 0; /* force lookup of first TB */
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for(;;) {
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#ifdef __sparc__
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/* g1 can be modified by some libc? functions */
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tmp_T0 = T0;
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#endif
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interrupt_request = env->interrupt_request;
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if (__builtin_expect(interrupt_request, 0)) {
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#if defined(TARGET_I386)
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/* if hardware interrupt pending, we execute it */
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->eflags & IF_MASK) &&
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!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
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int intno;
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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intno = cpu_get_pic_interrupt(env);
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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}
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do_interrupt(intno, 0, 0, 0, 1);
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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#ifdef __sparc__
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tmp_T0 = 0;
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#else
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T0 = 0;
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#endif
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}
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#elif defined(TARGET_PPC)
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#if 0
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if ((interrupt_request & CPU_INTERRUPT_RESET)) {
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cpu_ppc_reset(env);
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}
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#endif
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if (msr_ee != 0) {
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if ((interrupt_request & CPU_INTERRUPT_HARD)) {
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/* Raise it */
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env->exception_index = EXCP_EXTERNAL;
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env->error_code = 0;
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do_interrupt(env);
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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} else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
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/* Raise it */
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env->exception_index = EXCP_DECR;
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env->error_code = 0;
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do_interrupt(env);
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env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
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}
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}
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#elif defined(TARGET_SPARC)
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->psret != 0)) {
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int pil = env->interrupt_index & 15;
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int type = env->interrupt_index & 0xf0;
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if (((type == TT_EXTINT) &&
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(pil == 15 || pil > env->psrpil)) ||
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type != TT_EXTINT) {
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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do_interrupt(env->interrupt_index);
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env->interrupt_index = 0;
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}
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} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
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//do_interrupt(0, 0, 0, 0, 0);
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env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
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}
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#endif
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if (interrupt_request & CPU_INTERRUPT_EXITTB) {
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env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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#ifdef __sparc__
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tmp_T0 = 0;
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#else
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T0 = 0;
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#endif
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}
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if (interrupt_request & CPU_INTERRUPT_EXIT) {
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env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
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env->exception_index = EXCP_INTERRUPT;
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cpu_loop_exit();
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}
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}
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#ifdef DEBUG_EXEC
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if ((loglevel & CPU_LOG_EXEC)) {
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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#ifdef reg_EAX
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env->regs[R_EAX] = EAX;
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#endif
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#ifdef reg_EBX
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env->regs[R_EBX] = EBX;
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#endif
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#ifdef reg_ECX
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env->regs[R_ECX] = ECX;
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#endif
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#ifdef reg_EDX
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env->regs[R_EDX] = EDX;
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#endif
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#ifdef reg_ESI
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env->regs[R_ESI] = ESI;
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#endif
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#ifdef reg_EDI
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env->regs[R_EDI] = EDI;
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#endif
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#ifdef reg_EBP
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env->regs[R_EBP] = EBP;
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#endif
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#ifdef reg_ESP
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env->regs[R_ESP] = ESP;
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#endif
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
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cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_ARM)
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env->cpsr = compute_cpsr();
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cpu_dump_state(env, logfile, fprintf, 0);
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env->cpsr &= ~CACHED_CPSR_BITS;
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#elif defined(TARGET_SPARC)
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REGWPTR = env->regbase + (env->cwp * 16);
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env->regwptr = REGWPTR;
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cpu_dump_state(env, logfile, fprintf, 0);
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#elif defined(TARGET_PPC)
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cpu_dump_state(env, logfile, fprintf, 0);
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#else
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#error unsupported target CPU
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#endif
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}
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#endif
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/* we record a subset of the CPU state. It will
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always be the same before a given translated block
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is executed. */
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#if defined(TARGET_I386)
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flags = env->hflags;
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flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
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cs_base = env->segs[R_CS].base;
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pc = cs_base + env->eip;
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#elif defined(TARGET_ARM)
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flags = env->thumb | (env->vfp.vec_len << 1)
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| (env->vfp.vec_stride << 4);
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cs_base = 0;
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pc = env->regs[15];
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#elif defined(TARGET_SPARC)
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#ifdef TARGET_SPARC64
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flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
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#else
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flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
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#endif
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cs_base = env->npc;
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pc = env->pc;
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#elif defined(TARGET_PPC)
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flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
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(msr_se << MSR_SE) | (msr_le << MSR_LE);
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cs_base = 0;
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pc = env->nip;
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#else
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#error unsupported CPU
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#endif
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tb = tb_find(&ptb, pc, cs_base,
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flags);
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if (!tb) {
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TranslationBlock **ptb1;
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unsigned int h;
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target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
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|
|
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spin_lock(&tb_lock);
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|
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tb_invalidated_flag = 0;
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|
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regs_to_env(); /* XXX: do it just before cpu_gen_code() */
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|
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/* find translated block using physical mappings */
|
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phys_pc = get_phys_addr_code(env, pc);
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phys_page1 = phys_pc & TARGET_PAGE_MASK;
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phys_page2 = -1;
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h = tb_phys_hash_func(phys_pc);
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ptb1 = &tb_phys_hash[h];
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for(;;) {
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tb = *ptb1;
|
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if (!tb)
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goto not_found;
|
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if (tb->pc == pc &&
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tb->page_addr[0] == phys_page1 &&
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tb->cs_base == cs_base &&
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tb->flags == flags) {
|
|
/* check next page if needed */
|
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if (tb->page_addr[1] != -1) {
|
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virt_page2 = (pc & TARGET_PAGE_MASK) +
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TARGET_PAGE_SIZE;
|
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phys_page2 = get_phys_addr_code(env, virt_page2);
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if (tb->page_addr[1] == phys_page2)
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goto found;
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} else {
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goto found;
|
|
}
|
|
}
|
|
ptb1 = &tb->phys_hash_next;
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}
|
|
not_found:
|
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/* if no translated code available, then translate it now */
|
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tb = tb_alloc(pc);
|
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if (!tb) {
|
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/* flush must be done */
|
|
tb_flush(env);
|
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/* cannot fail at this point */
|
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tb = tb_alloc(pc);
|
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/* don't forget to invalidate previous TB info */
|
|
ptb = &tb_hash[tb_hash_func(pc)];
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T0 = 0;
|
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}
|
|
tc_ptr = code_gen_ptr;
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tb->tc_ptr = tc_ptr;
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tb->cs_base = cs_base;
|
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tb->flags = flags;
|
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cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
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|
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/* check next page if needed */
|
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virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
|
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phys_page2 = -1;
|
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if ((pc & TARGET_PAGE_MASK) != virt_page2) {
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phys_page2 = get_phys_addr_code(env, virt_page2);
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}
|
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tb_link_phys(tb, phys_pc, phys_page2);
|
|
|
|
found:
|
|
if (tb_invalidated_flag) {
|
|
/* as some TB could have been invalidated because
|
|
of memory exceptions while generating the code, we
|
|
must recompute the hash index here */
|
|
ptb = &tb_hash[tb_hash_func(pc)];
|
|
while (*ptb != NULL)
|
|
ptb = &(*ptb)->hash_next;
|
|
T0 = 0;
|
|
}
|
|
/* we add the TB in the virtual pc hash table */
|
|
*ptb = tb;
|
|
tb->hash_next = NULL;
|
|
tb_link(tb);
|
|
spin_unlock(&tb_lock);
|
|
}
|
|
#ifdef DEBUG_EXEC
|
|
if ((loglevel & CPU_LOG_EXEC)) {
|
|
fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
|
|
(long)tb->tc_ptr, tb->pc,
|
|
lookup_symbol(tb->pc));
|
|
}
|
|
#endif
|
|
#ifdef __sparc__
|
|
T0 = tmp_T0;
|
|
#endif
|
|
/* see if we can patch the calling TB. */
|
|
{
|
|
if (T0 != 0
|
|
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
|
&& (tb->cflags & CF_CODE_COPY) ==
|
|
(((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
|
#endif
|
|
) {
|
|
spin_lock(&tb_lock);
|
|
tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
|
|
#if defined(USE_CODE_COPY)
|
|
/* propagates the FP use info */
|
|
((TranslationBlock *)(T0 & ~3))->cflags |=
|
|
(tb->cflags & CF_FP_USED);
|
|
#endif
|
|
spin_unlock(&tb_lock);
|
|
}
|
|
}
|
|
tc_ptr = tb->tc_ptr;
|
|
env->current_tb = tb;
|
|
/* execute the generated code */
|
|
gen_func = (void *)tc_ptr;
|
|
#if defined(__sparc__)
|
|
__asm__ __volatile__("call %0\n\t"
|
|
"mov %%o7,%%i0"
|
|
: /* no outputs */
|
|
: "r" (gen_func)
|
|
: "i0", "i1", "i2", "i3", "i4", "i5");
|
|
#elif defined(__arm__)
|
|
asm volatile ("mov pc, %0\n\t"
|
|
".global exec_loop\n\t"
|
|
"exec_loop:\n\t"
|
|
: /* no outputs */
|
|
: "r" (gen_func)
|
|
: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
|
|
#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
|
{
|
|
if (!(tb->cflags & CF_CODE_COPY)) {
|
|
if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
|
save_native_fp_state(env);
|
|
}
|
|
gen_func();
|
|
} else {
|
|
if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
|
restore_native_fp_state(env);
|
|
}
|
|
/* we work with native eflags */
|
|
CC_SRC = cc_table[CC_OP].compute_all();
|
|
CC_OP = CC_OP_EFLAGS;
|
|
asm(".globl exec_loop\n"
|
|
"\n"
|
|
"debug1:\n"
|
|
" pushl %%ebp\n"
|
|
" fs movl %10, %9\n"
|
|
" fs movl %11, %%eax\n"
|
|
" andl $0x400, %%eax\n"
|
|
" fs orl %8, %%eax\n"
|
|
" pushl %%eax\n"
|
|
" popf\n"
|
|
" fs movl %%esp, %12\n"
|
|
" fs movl %0, %%eax\n"
|
|
" fs movl %1, %%ecx\n"
|
|
" fs movl %2, %%edx\n"
|
|
" fs movl %3, %%ebx\n"
|
|
" fs movl %4, %%esp\n"
|
|
" fs movl %5, %%ebp\n"
|
|
" fs movl %6, %%esi\n"
|
|
" fs movl %7, %%edi\n"
|
|
" fs jmp *%9\n"
|
|
"exec_loop:\n"
|
|
" fs movl %%esp, %4\n"
|
|
" fs movl %12, %%esp\n"
|
|
" fs movl %%eax, %0\n"
|
|
" fs movl %%ecx, %1\n"
|
|
" fs movl %%edx, %2\n"
|
|
" fs movl %%ebx, %3\n"
|
|
" fs movl %%ebp, %5\n"
|
|
" fs movl %%esi, %6\n"
|
|
" fs movl %%edi, %7\n"
|
|
" pushf\n"
|
|
" popl %%eax\n"
|
|
" movl %%eax, %%ecx\n"
|
|
" andl $0x400, %%ecx\n"
|
|
" shrl $9, %%ecx\n"
|
|
" andl $0x8d5, %%eax\n"
|
|
" fs movl %%eax, %8\n"
|
|
" movl $1, %%eax\n"
|
|
" subl %%ecx, %%eax\n"
|
|
" fs movl %%eax, %11\n"
|
|
" fs movl %9, %%ebx\n" /* get T0 value */
|
|
" popl %%ebp\n"
|
|
:
|
|
: "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[1])),
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[2])),
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[3])),
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[4])),
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[5])),
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[6])),
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[7])),
|
|
"m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
|
"m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
|
"a" (gen_func),
|
|
"m" (*(uint8_t *)offsetof(CPUState, df)),
|
|
"m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
|
: "%ecx", "%edx"
|
|
);
|
|
}
|
|
}
|
|
#elif defined(__ia64)
|
|
struct fptr {
|
|
void *ip;
|
|
void *gp;
|
|
} fp;
|
|
|
|
fp.ip = tc_ptr;
|
|
fp.gp = code_gen_buffer + 2 * (1 << 20);
|
|
(*(void (*)(void)) &fp)();
|
|
#else
|
|
gen_func();
|
|
#endif
|
|
env->current_tb = NULL;
|
|
/* reset soft MMU for next block (it can currently
|
|
only be set by a memory fault) */
|
|
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
|
if (env->hflags & HF_SOFTMMU_MASK) {
|
|
env->hflags &= ~HF_SOFTMMU_MASK;
|
|
/* do not allow linking to another block */
|
|
T0 = 0;
|
|
}
|
|
#endif
|
|
}
|
|
} else {
|
|
env_to_regs();
|
|
}
|
|
} /* for(;;) */
|
|
|
|
|
|
#if defined(TARGET_I386)
|
|
#if defined(USE_CODE_COPY)
|
|
if (env->native_fp_regs) {
|
|
save_native_fp_state(env);
|
|
}
|
|
#endif
|
|
/* restore flags in standard format */
|
|
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
|
|
|
|
/* restore global registers */
|
|
#ifdef reg_EAX
|
|
EAX = saved_EAX;
|
|
#endif
|
|
#ifdef reg_ECX
|
|
ECX = saved_ECX;
|
|
#endif
|
|
#ifdef reg_EDX
|
|
EDX = saved_EDX;
|
|
#endif
|
|
#ifdef reg_EBX
|
|
EBX = saved_EBX;
|
|
#endif
|
|
#ifdef reg_ESP
|
|
ESP = saved_ESP;
|
|
#endif
|
|
#ifdef reg_EBP
|
|
EBP = saved_EBP;
|
|
#endif
|
|
#ifdef reg_ESI
|
|
ESI = saved_ESI;
|
|
#endif
|
|
#ifdef reg_EDI
|
|
EDI = saved_EDI;
|
|
#endif
|
|
#elif defined(TARGET_ARM)
|
|
env->cpsr = compute_cpsr();
|
|
/* XXX: Save/restore host fpu exception state?. */
|
|
#elif defined(TARGET_SPARC)
|
|
#if defined(reg_REGWPTR)
|
|
REGWPTR = saved_regwptr;
|
|
#endif
|
|
#elif defined(TARGET_PPC)
|
|
#else
|
|
#error unsupported target CPU
|
|
#endif
|
|
#ifdef __sparc__
|
|
asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
|
|
#endif
|
|
T0 = saved_T0;
|
|
T1 = saved_T1;
|
|
#if defined(reg_T2)
|
|
T2 = saved_T2;
|
|
#endif
|
|
env = saved_env;
|
|
return ret;
|
|
}
|
|
|
|
/* must only be called from the generated code as an exception can be
|
|
generated */
|
|
void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
|
{
|
|
/* XXX: cannot enable it yet because it yields to MMU exception
|
|
where NIP != read address on PowerPC */
|
|
#if 0
|
|
target_ulong phys_addr;
|
|
phys_addr = get_phys_addr_code(env, start);
|
|
tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
|
#endif
|
|
}
|
|
|
|
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
|
|
|
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
|
|
{
|
|
CPUX86State *saved_env;
|
|
|
|
saved_env = env;
|
|
env = s;
|
|
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
|
|
selector &= 0xffff;
|
|
cpu_x86_load_seg_cache(env, seg_reg, selector,
|
|
(selector << 4), 0xffff, 0);
|
|
} else {
|
|
load_seg(seg_reg, selector);
|
|
}
|
|
env = saved_env;
|
|
}
|
|
|
|
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
|
|
{
|
|
CPUX86State *saved_env;
|
|
|
|
saved_env = env;
|
|
env = s;
|
|
|
|
helper_fsave((target_ulong)ptr, data32);
|
|
|
|
env = saved_env;
|
|
}
|
|
|
|
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
|
|
{
|
|
CPUX86State *saved_env;
|
|
|
|
saved_env = env;
|
|
env = s;
|
|
|
|
helper_frstor((target_ulong)ptr, data32);
|
|
|
|
env = saved_env;
|
|
}
|
|
|
|
#endif /* TARGET_I386 */
|
|
|
|
#if !defined(CONFIG_SOFTMMU)
|
|
|
|
#if defined(TARGET_I386)
|
|
|
|
/* 'pc' is the host PC at which the exception was raised. 'address' is
|
|
the effective address of the memory exception. 'is_write' is 1 if a
|
|
write caused the exception and otherwise 0'. 'old_set' is the
|
|
signal set which should be restored */
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
|
int is_write, sigset_t *old_set,
|
|
void *puc)
|
|
{
|
|
TranslationBlock *tb;
|
|
int ret;
|
|
|
|
if (cpu_single_env)
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
#if defined(DEBUG_SIGNAL)
|
|
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
#endif
|
|
/* XXX: locking issue */
|
|
if (is_write && page_unprotect(address, pc, puc)) {
|
|
return 1;
|
|
}
|
|
|
|
/* see if it is an MMU fault */
|
|
ret = cpu_x86_handle_mmu_fault(env, address, is_write,
|
|
((env->hflags & HF_CPL_MASK) == 3), 0);
|
|
if (ret < 0)
|
|
return 0; /* not an MMU fault */
|
|
if (ret == 0)
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
/* now we have a real cpu fault */
|
|
tb = tb_find_pc(pc);
|
|
if (tb) {
|
|
/* the PC is inside the translated code. It means that we have
|
|
a virtual CPU fault */
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
}
|
|
if (ret == 1) {
|
|
#if 0
|
|
printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
|
env->eip, env->cr[2], env->error_code);
|
|
#endif
|
|
/* we restore the process signal mask as the sigreturn should
|
|
do it (XXX: use sigsetjmp) */
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
raise_exception_err(EXCP0E_PAGE, env->error_code);
|
|
} else {
|
|
/* activate soft MMU for this block */
|
|
env->hflags |= HF_SOFTMMU_MASK;
|
|
cpu_resume_from_signal(env, puc);
|
|
}
|
|
/* never comes here */
|
|
return 1;
|
|
}
|
|
|
|
#elif defined(TARGET_ARM)
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
|
int is_write, sigset_t *old_set,
|
|
void *puc)
|
|
{
|
|
TranslationBlock *tb;
|
|
int ret;
|
|
|
|
if (cpu_single_env)
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
#if defined(DEBUG_SIGNAL)
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
#endif
|
|
/* XXX: locking issue */
|
|
if (is_write && page_unprotect(address, pc, puc)) {
|
|
return 1;
|
|
}
|
|
/* see if it is an MMU fault */
|
|
ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
|
|
if (ret < 0)
|
|
return 0; /* not an MMU fault */
|
|
if (ret == 0)
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
/* now we have a real cpu fault */
|
|
tb = tb_find_pc(pc);
|
|
if (tb) {
|
|
/* the PC is inside the translated code. It means that we have
|
|
a virtual CPU fault */
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
}
|
|
/* we restore the process signal mask as the sigreturn should
|
|
do it (XXX: use sigsetjmp) */
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
cpu_loop_exit();
|
|
}
|
|
#elif defined(TARGET_SPARC)
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
|
int is_write, sigset_t *old_set,
|
|
void *puc)
|
|
{
|
|
TranslationBlock *tb;
|
|
int ret;
|
|
|
|
if (cpu_single_env)
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
#if defined(DEBUG_SIGNAL)
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
#endif
|
|
/* XXX: locking issue */
|
|
if (is_write && page_unprotect(address, pc, puc)) {
|
|
return 1;
|
|
}
|
|
/* see if it is an MMU fault */
|
|
ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
|
|
if (ret < 0)
|
|
return 0; /* not an MMU fault */
|
|
if (ret == 0)
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
/* now we have a real cpu fault */
|
|
tb = tb_find_pc(pc);
|
|
if (tb) {
|
|
/* the PC is inside the translated code. It means that we have
|
|
a virtual CPU fault */
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
}
|
|
/* we restore the process signal mask as the sigreturn should
|
|
do it (XXX: use sigsetjmp) */
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
cpu_loop_exit();
|
|
}
|
|
#elif defined (TARGET_PPC)
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
|
int is_write, sigset_t *old_set,
|
|
void *puc)
|
|
{
|
|
TranslationBlock *tb;
|
|
int ret;
|
|
|
|
if (cpu_single_env)
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
#if defined(DEBUG_SIGNAL)
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
#endif
|
|
/* XXX: locking issue */
|
|
if (is_write && page_unprotect(address, pc, puc)) {
|
|
return 1;
|
|
}
|
|
|
|
/* see if it is an MMU fault */
|
|
ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
|
if (ret < 0)
|
|
return 0; /* not an MMU fault */
|
|
if (ret == 0)
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
|
|
/* now we have a real cpu fault */
|
|
tb = tb_find_pc(pc);
|
|
if (tb) {
|
|
/* the PC is inside the translated code. It means that we have
|
|
a virtual CPU fault */
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
}
|
|
if (ret == 1) {
|
|
#if 0
|
|
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
|
env->nip, env->error_code, tb);
|
|
#endif
|
|
/* we restore the process signal mask as the sigreturn should
|
|
do it (XXX: use sigsetjmp) */
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
do_raise_exception_err(env->exception_index, env->error_code);
|
|
} else {
|
|
/* activate soft MMU for this block */
|
|
cpu_resume_from_signal(env, puc);
|
|
}
|
|
/* never comes here */
|
|
return 1;
|
|
}
|
|
#else
|
|
#error unsupported target CPU
|
|
#endif
|
|
|
|
#if defined(__i386__)
|
|
|
|
#if defined(USE_CODE_COPY)
|
|
static void cpu_send_trap(unsigned long pc, int trap,
|
|
struct ucontext *uc)
|
|
{
|
|
TranslationBlock *tb;
|
|
|
|
if (cpu_single_env)
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
/* now we have a real cpu fault */
|
|
tb = tb_find_pc(pc);
|
|
if (tb) {
|
|
/* the PC is inside the translated code. It means that we have
|
|
a virtual CPU fault */
|
|
cpu_restore_state(tb, env, pc, uc);
|
|
}
|
|
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
|
raise_exception_err(trap, env->error_code);
|
|
}
|
|
#endif
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int trapno;
|
|
|
|
#ifndef REG_EIP
|
|
/* for glibc 2.1 */
|
|
#define REG_EIP EIP
|
|
#define REG_ERR ERR
|
|
#define REG_TRAPNO TRAPNO
|
|
#endif
|
|
pc = uc->uc_mcontext.gregs[REG_EIP];
|
|
trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
|
|
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
|
if (trapno == 0x00 || trapno == 0x05) {
|
|
/* send division by zero or bound exception */
|
|
cpu_send_trap(pc, trapno, uc);
|
|
return 1;
|
|
} else
|
|
#endif
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
trapno == 0xe ?
|
|
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
|
|
&uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__x86_64__)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
|
|
pc = uc->uc_mcontext.gregs[REG_RIP];
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
|
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
|
|
&uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__powerpc__)
|
|
|
|
/***********************************************************************
|
|
* signal context platform-specific definitions
|
|
* From Wine
|
|
*/
|
|
#ifdef linux
|
|
/* All Registers access - only for local access */
|
|
# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
|
/* Gpr Registers access */
|
|
# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
|
# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
|
|
# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
|
|
# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
|
|
# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
|
|
# define LR_sig(context) REG_sig(link, context) /* Link register */
|
|
# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
|
|
/* Float Registers access */
|
|
# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
|
|
# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
|
|
/* Exception Registers access */
|
|
# define DAR_sig(context) REG_sig(dar, context)
|
|
# define DSISR_sig(context) REG_sig(dsisr, context)
|
|
# define TRAP_sig(context) REG_sig(trap, context)
|
|
#endif /* linux */
|
|
|
|
#ifdef __APPLE__
|
|
# include <sys/ucontext.h>
|
|
typedef struct ucontext SIGCONTEXT;
|
|
/* All Registers access - only for local access */
|
|
# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
|
# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
|
# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
|
# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
|
/* Gpr Registers access */
|
|
# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
|
|
# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
|
|
# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
|
|
# define CTR_sig(context) REG_sig(ctr, context)
|
|
# define XER_sig(context) REG_sig(xer, context) /* Link register */
|
|
# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
|
|
# define CR_sig(context) REG_sig(cr, context) /* Condition register */
|
|
/* Float Registers access */
|
|
# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
|
# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
|
|
/* Exception Registers access */
|
|
# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
|
|
# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
|
# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
|
|
#endif /* __APPLE__ */
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = IAR_sig(uc);
|
|
is_write = 0;
|
|
#if 0
|
|
/* ppc 4xx case */
|
|
if (DSISR_sig(uc) & 0x00800000)
|
|
is_write = 1;
|
|
#else
|
|
if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
|
|
is_write = 1;
|
|
#endif
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, &uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__alpha__)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
uint32_t *pc = uc->uc_mcontext.sc_pc;
|
|
uint32_t insn = *pc;
|
|
int is_write = 0;
|
|
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
switch (insn >> 26) {
|
|
case 0x0d: // stw
|
|
case 0x0e: // stb
|
|
case 0x0f: // stq_u
|
|
case 0x24: // stf
|
|
case 0x25: // stg
|
|
case 0x26: // sts
|
|
case 0x27: // stt
|
|
case 0x2c: // stl
|
|
case 0x2d: // stq
|
|
case 0x2e: // stl_c
|
|
case 0x2f: // stq_c
|
|
is_write = 1;
|
|
}
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, &uc->uc_sigmask, puc);
|
|
}
|
|
#elif defined(__sparc__)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
uint32_t *regs = (uint32_t *)(info + 1);
|
|
void *sigmask = (regs + 20);
|
|
unsigned long pc;
|
|
int is_write;
|
|
uint32_t insn;
|
|
|
|
/* XXX: is there a standard glibc define ? */
|
|
pc = regs[1];
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
is_write = 0;
|
|
insn = *(uint32_t *)pc;
|
|
if ((insn >> 30) == 3) {
|
|
switch((insn >> 19) & 0x3f) {
|
|
case 0x05: // stb
|
|
case 0x06: // sth
|
|
case 0x04: // st
|
|
case 0x07: // std
|
|
case 0x24: // stf
|
|
case 0x27: // stdf
|
|
case 0x25: // stfsr
|
|
is_write = 1;
|
|
break;
|
|
}
|
|
}
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write, sigmask, NULL);
|
|
}
|
|
|
|
#elif defined(__arm__)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = uc->uc_mcontext.gregs[R15];
|
|
/* XXX: compute is_write */
|
|
is_write = 0;
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write,
|
|
&uc->uc_sigmask);
|
|
}
|
|
|
|
#elif defined(__mc68000)
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info,
|
|
void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
unsigned long pc;
|
|
int is_write;
|
|
|
|
pc = uc->uc_mcontext.gregs[16];
|
|
/* XXX: compute is_write */
|
|
is_write = 0;
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
is_write,
|
|
&uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#elif defined(__ia64)
|
|
|
|
#ifndef __ISR_VALID
|
|
/* This ought to be in <bits/siginfo.h>... */
|
|
# define __ISR_VALID 1
|
|
# define si_flags _sifields._sigfault._si_pad0
|
|
#endif
|
|
|
|
int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
|
|
{
|
|
struct ucontext *uc = puc;
|
|
unsigned long ip;
|
|
int is_write = 0;
|
|
|
|
ip = uc->uc_mcontext.sc_ip;
|
|
switch (host_signum) {
|
|
case SIGILL:
|
|
case SIGFPE:
|
|
case SIGSEGV:
|
|
case SIGBUS:
|
|
case SIGTRAP:
|
|
if (info->si_code && (info->si_flags & __ISR_VALID))
|
|
/* ISR.W (write-access) is bit 33: */
|
|
is_write = (info->si_isr >> 33) & 1;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
return handle_cpu_signal(ip, (unsigned long)info->si_addr,
|
|
is_write,
|
|
&uc->uc_sigmask, puc);
|
|
}
|
|
|
|
#else
|
|
|
|
#error host CPU specific signal handler needed
|
|
|
|
#endif
|
|
|
|
#endif /* !defined(CONFIG_SOFTMMU) */
|