5fafdf24ef
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
338 lines
9.2 KiB
C
338 lines
9.2 KiB
C
/*
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* m68k op helpers
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*
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* Copyright (c) 2006-2007 CodeSourcery
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* Written by Paul Brook
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdio.h>
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#include <string.h>
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#include "config.h"
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#include "cpu.h"
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#include "exec-all.h"
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enum m68k_cpuid {
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M68K_CPUID_M5206,
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M68K_CPUID_M5208,
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M68K_CPUID_CFV4E,
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M68K_CPUID_ANY,
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};
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struct m68k_def_t {
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const char * name;
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enum m68k_cpuid id;
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};
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static m68k_def_t m68k_cpu_defs[] = {
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{"m5206", M68K_CPUID_M5206},
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{"m5208", M68K_CPUID_M5208},
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{"cfv4e", M68K_CPUID_CFV4E},
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{"any", M68K_CPUID_ANY},
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{NULL, 0},
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};
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static void m68k_set_feature(CPUM68KState *env, int feature)
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{
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env->features |= (1u << feature);
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}
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int cpu_m68k_set_model(CPUM68KState *env, const char * name)
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{
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m68k_def_t *def;
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for (def = m68k_cpu_defs; def->name; def++) {
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if (strcmp(def->name, name) == 0)
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break;
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}
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if (!def->name)
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return 1;
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switch (def->id) {
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case M68K_CPUID_M5206:
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
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break;
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case M68K_CPUID_M5208:
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
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m68k_set_feature(env, M68K_FEATURE_BRAL);
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m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
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m68k_set_feature(env, M68K_FEATURE_USP);
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break;
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case M68K_CPUID_CFV4E:
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
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m68k_set_feature(env, M68K_FEATURE_BRAL);
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m68k_set_feature(env, M68K_FEATURE_CF_FPU);
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m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
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m68k_set_feature(env, M68K_FEATURE_USP);
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break;
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case M68K_CPUID_ANY:
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_B);
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m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC);
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m68k_set_feature(env, M68K_FEATURE_BRAL);
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m68k_set_feature(env, M68K_FEATURE_CF_FPU);
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/* MAC and EMAC are mututally exclusive, so pick EMAC.
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It's mostly backwards compatible. */
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m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
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m68k_set_feature(env, M68K_FEATURE_CF_EMAC_B);
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m68k_set_feature(env, M68K_FEATURE_USP);
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m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
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m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
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break;
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}
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register_m68k_insns(env);
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return 0;
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}
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void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
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{
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int flags;
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uint32_t src;
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uint32_t dest;
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uint32_t tmp;
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#define HIGHBIT 0x80000000u
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#define SET_NZ(x) do { \
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if ((x) == 0) \
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flags |= CCF_Z; \
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else if ((int32_t)(x) < 0) \
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flags |= CCF_N; \
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} while (0)
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#define SET_FLAGS_SUB(type, utype) do { \
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SET_NZ((type)dest); \
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tmp = dest + src; \
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if ((utype) tmp < (utype) src) \
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flags |= CCF_C; \
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if ((1u << (sizeof(type) * 8 - 1)) & (tmp ^ dest) & (tmp ^ src)) \
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flags |= CCF_V; \
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} while (0)
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flags = 0;
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src = env->cc_src;
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dest = env->cc_dest;
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switch (cc_op) {
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case CC_OP_FLAGS:
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flags = dest;
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break;
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case CC_OP_LOGIC:
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SET_NZ(dest);
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break;
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case CC_OP_ADD:
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SET_NZ(dest);
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if (dest < src)
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flags |= CCF_C;
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tmp = dest - src;
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if (HIGHBIT & (src ^ dest) & ~(tmp ^ src))
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flags |= CCF_V;
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break;
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case CC_OP_SUB:
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SET_FLAGS_SUB(int32_t, uint32_t);
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break;
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case CC_OP_CMPB:
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SET_FLAGS_SUB(int8_t, uint8_t);
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break;
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case CC_OP_CMPW:
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SET_FLAGS_SUB(int16_t, uint16_t);
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break;
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case CC_OP_ADDX:
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SET_NZ(dest);
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if (dest <= src)
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flags |= CCF_C;
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tmp = dest - src - 1;
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if (HIGHBIT & (src ^ dest) & ~(tmp ^ src))
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flags |= CCF_V;
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break;
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case CC_OP_SUBX:
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SET_NZ(dest);
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tmp = dest + src + 1;
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if (tmp <= src)
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flags |= CCF_C;
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if (HIGHBIT & (tmp ^ dest) & (tmp ^ src))
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flags |= CCF_V;
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break;
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case CC_OP_SHL:
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if (src >= 32) {
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SET_NZ(0);
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} else {
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tmp = dest << src;
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SET_NZ(tmp);
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}
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if (src && src <= 32 && (dest & (1 << (32 - src))))
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flags |= CCF_C;
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break;
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case CC_OP_SHR:
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if (src >= 32) {
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SET_NZ(0);
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} else {
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tmp = dest >> src;
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SET_NZ(tmp);
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}
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if (src && src <= 32 && ((dest >> (src - 1)) & 1))
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flags |= CCF_C;
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break;
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case CC_OP_SAR:
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if (src >= 32) {
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SET_NZ(-1);
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} else {
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tmp = (int32_t)dest >> src;
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SET_NZ(tmp);
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}
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if (src && src <= 32 && (((int32_t)dest >> (src - 1)) & 1))
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flags |= CCF_C;
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break;
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default:
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cpu_abort(env, "Bad CC_OP %d", cc_op);
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}
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env->cc_op = CC_OP_FLAGS;
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env->cc_dest = flags;
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}
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float64 helper_sub_cmpf64(CPUM68KState *env, float64 src0, float64 src1)
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{
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/* ??? This may incorrectly raise exceptions. */
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/* ??? Should flush denormals to zero. */
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float64 res;
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res = float64_sub(src0, src1, &env->fp_status);
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if (float64_is_nan(res)) {
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/* +/-inf compares equal against itself, but sub returns nan. */
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if (!float64_is_nan(src0)
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&& !float64_is_nan(src1)) {
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res = 0;
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if (float64_lt_quiet(src0, res, &env->fp_status))
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res = float64_chs(res);
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}
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}
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return res;
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}
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void helper_movec(CPUM68KState *env, int reg, uint32_t val)
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{
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switch (reg) {
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case 0x02: /* CACR */
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env->cacr = val;
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m68k_switch_sp(env);
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break;
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case 0x04: case 0x05: case 0x06: case 0x07: /* ACR[0-3] */
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/* TODO: Implement Access Control Registers. */
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break;
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case 0x801: /* VBR */
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env->vbr = val;
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break;
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/* TODO: Implement control registers. */
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default:
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cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n",
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reg, val);
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}
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}
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void m68k_set_macsr(CPUM68KState *env, uint32_t val)
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{
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uint32_t acc;
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int8_t exthigh;
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uint8_t extlow;
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uint64_t regval;
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int i;
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if ((env->macsr ^ val) & (MACSR_FI | MACSR_SU)) {
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for (i = 0; i < 4; i++) {
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regval = env->macc[i];
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exthigh = regval >> 40;
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if (env->macsr & MACSR_FI) {
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acc = regval >> 8;
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extlow = regval;
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} else {
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acc = regval;
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extlow = regval >> 32;
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}
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if (env->macsr & MACSR_FI) {
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regval = (((uint64_t)acc) << 8) | extlow;
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regval |= ((int64_t)exthigh) << 40;
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} else if (env->macsr & MACSR_SU) {
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regval = acc | (((int64_t)extlow) << 32);
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regval |= ((int64_t)exthigh) << 40;
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} else {
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regval = acc | (((uint64_t)extlow) << 32);
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regval |= ((uint64_t)(uint8_t)exthigh) << 40;
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}
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env->macc[i] = regval;
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}
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}
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env->macsr = val;
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}
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void m68k_switch_sp(CPUM68KState *env)
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{
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int new_sp;
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env->sp[env->current_sp] = env->aregs[7];
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new_sp = (env->sr & SR_S && env->cacr & M68K_CACR_EUSP)
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? M68K_SSP : M68K_USP;
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env->aregs[7] = env->sp[new_sp];
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env->current_sp = new_sp;
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}
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/* MMU */
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/* TODO: This will need fixing once the MMU is implemented. */
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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return addr;
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}
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#if defined(CONFIG_USER_ONLY)
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int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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env->exception_index = EXCP_ACCESS;
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env->mmu.ar = address;
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return 1;
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}
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#else
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int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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int prot;
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address &= TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE;
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return tlb_set_page(env, address, address, prot, is_user, is_softmmu);
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}
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/* Notify CPU of a pending interrupt. Prioritization and vectoring should
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be handled by the interrupt controller. Real hardware only requests
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the vector when the interrupt is acknowledged by the CPU. For
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simplicitly we calculate it when the interrupt is signalled. */
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void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector)
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{
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env->pending_level = level;
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env->pending_vector = vector;
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if (level)
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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#endif
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