qemu/target/mips/tcg
Richard Henderson 92ecfab50e target/mips: Fix gen_mxu_s32ldd_s32lddr
There were two bugs here: (1) the required endianness was
not present in the MemOp, and (2) we were not providing a
zero-extended input to the bswap as semantics required.

The best fix is to fold the bswap into the memory operation,
producing the desired result directly.

Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-29 10:04:57 -07:00
..
sysemu
user
dsp_helper.c
exception.c
fpu_helper.c
ldst_helper.c
lmmi_helper.c
meson.build
mips32r6.decode
mips64r6.decode
msa.decode
msa_helper.c
msa_helper.h.inc
msa_translate.c
mxu_translate.c target/mips: Fix gen_mxu_s32ldd_s32lddr 2021-06-29 10:04:57 -07:00
op_helper.c
rel6_translate.c
sysemu_helper.h.inc
tcg-internal.h
trace-events
trace.h
translate.c
translate.h
translate_addr_const.c
tx79.decode
tx79_translate.c
txx9_translate.c