330d2ae32a
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
575 lines
18 KiB
C
575 lines
18 KiB
C
/* RISC-V ISA constants */
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#ifndef TARGET_RISCV_CPU_BITS_H
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#define TARGET_RISCV_CPU_BITS_H
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#define get_field(reg, mask) (((reg) & \
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(uint64_t)(mask)) / ((mask) & ~((mask) << 1)))
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#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \
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(((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \
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(uint64_t)(mask)))
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/* Floating point round mode */
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#define FSR_RD_SHIFT 5
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#define FSR_RD (0x7 << FSR_RD_SHIFT)
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/* Floating point accrued exception flags */
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#define FPEXC_NX 0x01
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#define FPEXC_UF 0x02
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#define FPEXC_OF 0x04
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#define FPEXC_DZ 0x08
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#define FPEXC_NV 0x10
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/* Floating point status register bits */
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#define FSR_AEXC_SHIFT 0
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#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
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#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
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#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
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#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
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#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
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#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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/* Vector Fixed-Point round model */
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#define FSR_VXRM_SHIFT 9
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#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT)
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/* Vector Fixed-Point saturation flag */
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#define FSR_VXSAT_SHIFT 8
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#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT)
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/* Control and Status Registers */
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/* User Trap Setup */
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#define CSR_USTATUS 0x000
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#define CSR_UIE 0x004
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#define CSR_UTVEC 0x005
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/* User Trap Handling */
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#define CSR_USCRATCH 0x040
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#define CSR_UEPC 0x041
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#define CSR_UCAUSE 0x042
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#define CSR_UTVAL 0x043
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#define CSR_UIP 0x044
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/* User Floating-Point CSRs */
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#define CSR_FFLAGS 0x001
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#define CSR_FRM 0x002
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#define CSR_FCSR 0x003
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/* User Vector CSRs */
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#define CSR_VSTART 0x008
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#define CSR_VXSAT 0x009
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#define CSR_VXRM 0x00a
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#define CSR_VL 0xc20
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#define CSR_VTYPE 0xc21
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/* User Timers and Counters */
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_HPMCOUNTER3 0xc03
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#define CSR_HPMCOUNTER4 0xc04
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#define CSR_HPMCOUNTER5 0xc05
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#define CSR_HPMCOUNTER6 0xc06
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#define CSR_HPMCOUNTER7 0xc07
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#define CSR_HPMCOUNTER8 0xc08
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#define CSR_HPMCOUNTER9 0xc09
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#define CSR_HPMCOUNTER10 0xc0a
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#define CSR_HPMCOUNTER11 0xc0b
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#define CSR_HPMCOUNTER12 0xc0c
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#define CSR_HPMCOUNTER13 0xc0d
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#define CSR_HPMCOUNTER14 0xc0e
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#define CSR_HPMCOUNTER15 0xc0f
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#define CSR_HPMCOUNTER16 0xc10
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#define CSR_HPMCOUNTER17 0xc11
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#define CSR_HPMCOUNTER18 0xc12
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#define CSR_HPMCOUNTER19 0xc13
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#define CSR_HPMCOUNTER20 0xc14
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#define CSR_HPMCOUNTER21 0xc15
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#define CSR_HPMCOUNTER22 0xc16
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#define CSR_HPMCOUNTER23 0xc17
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#define CSR_HPMCOUNTER24 0xc18
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#define CSR_HPMCOUNTER25 0xc19
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#define CSR_HPMCOUNTER26 0xc1a
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#define CSR_HPMCOUNTER27 0xc1b
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#define CSR_HPMCOUNTER28 0xc1c
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#define CSR_HPMCOUNTER29 0xc1d
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#define CSR_HPMCOUNTER30 0xc1e
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#define CSR_HPMCOUNTER31 0xc1f
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_HPMCOUNTER3H 0xc83
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#define CSR_HPMCOUNTER4H 0xc84
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#define CSR_HPMCOUNTER5H 0xc85
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#define CSR_HPMCOUNTER6H 0xc86
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#define CSR_HPMCOUNTER7H 0xc87
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#define CSR_HPMCOUNTER8H 0xc88
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#define CSR_HPMCOUNTER9H 0xc89
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#define CSR_HPMCOUNTER10H 0xc8a
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#define CSR_HPMCOUNTER11H 0xc8b
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#define CSR_HPMCOUNTER12H 0xc8c
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#define CSR_HPMCOUNTER13H 0xc8d
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#define CSR_HPMCOUNTER14H 0xc8e
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#define CSR_HPMCOUNTER15H 0xc8f
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#define CSR_HPMCOUNTER16H 0xc90
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#define CSR_HPMCOUNTER17H 0xc91
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#define CSR_HPMCOUNTER18H 0xc92
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#define CSR_HPMCOUNTER19H 0xc93
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#define CSR_HPMCOUNTER20H 0xc94
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#define CSR_HPMCOUNTER21H 0xc95
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#define CSR_HPMCOUNTER22H 0xc96
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#define CSR_HPMCOUNTER23H 0xc97
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#define CSR_HPMCOUNTER24H 0xc98
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#define CSR_HPMCOUNTER25H 0xc99
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#define CSR_HPMCOUNTER26H 0xc9a
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#define CSR_HPMCOUNTER27H 0xc9b
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#define CSR_HPMCOUNTER28H 0xc9c
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#define CSR_HPMCOUNTER29H 0xc9d
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#define CSR_HPMCOUNTER30H 0xc9e
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#define CSR_HPMCOUNTER31H 0xc9f
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/* Machine Timers and Counters */
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#define CSR_MCYCLE 0xb00
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#define CSR_MINSTRET 0xb02
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#define CSR_MCYCLEH 0xb80
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#define CSR_MINSTRETH 0xb82
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/* Machine Information Registers */
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#define CSR_MVENDORID 0xf11
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#define CSR_MARCHID 0xf12
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#define CSR_MIMPID 0xf13
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#define CSR_MHARTID 0xf14
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/* Machine Trap Setup */
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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/* 32-bit only */
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#define CSR_MSTATUSH 0x310
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/* Machine Trap Handling */
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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/* Supervisor Trap Setup */
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#define CSR_SSTATUS 0x100
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#define CSR_SEDELEG 0x102
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#define CSR_SIDELEG 0x103
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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/* Supervisor Trap Handling */
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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/* Supervisor Protection and Translation */
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#define CSR_SPTBR 0x180
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#define CSR_SATP 0x180
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/* Hpervisor CSRs */
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#define CSR_HSTATUS 0x600
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#define CSR_HEDELEG 0x602
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#define CSR_HIDELEG 0x603
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#define CSR_HIE 0x604
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#define CSR_HCOUNTEREN 0x606
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#define CSR_HGEIE 0x607
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#define CSR_HTVAL 0x643
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#define CSR_HVIP 0x645
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#define CSR_HIP 0x644
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#define CSR_HTINST 0x64A
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#define CSR_HGEIP 0xE12
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#define CSR_HGATP 0x680
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#define CSR_HTIMEDELTA 0x605
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#define CSR_HTIMEDELTAH 0x615
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#if defined(TARGET_RISCV32)
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#define HGATP_MODE SATP32_MODE
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#define HGATP_VMID SATP32_ASID
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#define HGATP_PPN SATP32_PPN
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#endif
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#if defined(TARGET_RISCV64)
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#define HGATP_MODE SATP64_MODE
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#define HGATP_VMID SATP64_ASID
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#define HGATP_PPN SATP64_PPN
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#endif
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/* Virtual CSRs */
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#define CSR_VSSTATUS 0x200
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#define CSR_VSIE 0x204
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#define CSR_VSTVEC 0x205
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#define CSR_VSSCRATCH 0x240
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#define CSR_VSEPC 0x241
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#define CSR_VSCAUSE 0x242
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#define CSR_VSTVAL 0x243
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#define CSR_VSIP 0x244
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#define CSR_VSATP 0x280
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#define CSR_MTINST 0x34a
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#define CSR_MTVAL2 0x34b
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/* Physical Memory Protection */
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPCFG1 0x3a1
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#define CSR_PMPCFG2 0x3a2
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#define CSR_PMPCFG3 0x3a3
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#define CSR_PMPADDR0 0x3b0
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#define CSR_PMPADDR1 0x3b1
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#define CSR_PMPADDR2 0x3b2
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#define CSR_PMPADDR3 0x3b3
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#define CSR_PMPADDR4 0x3b4
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#define CSR_PMPADDR5 0x3b5
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#define CSR_PMPADDR6 0x3b6
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#define CSR_PMPADDR7 0x3b7
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#define CSR_PMPADDR8 0x3b8
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#define CSR_PMPADDR9 0x3b9
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#define CSR_PMPADDR10 0x3ba
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#define CSR_PMPADDR11 0x3bb
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#define CSR_PMPADDR12 0x3bc
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#define CSR_PMPADDR13 0x3bd
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#define CSR_PMPADDR14 0x3be
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#define CSR_PMPADDR15 0x3bf
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/* Debug/Trace Registers (shared with Debug Mode) */
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#define CSR_TSELECT 0x7a0
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#define CSR_TDATA1 0x7a1
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#define CSR_TDATA2 0x7a2
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#define CSR_TDATA3 0x7a3
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/* Debug Mode Registers */
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#define CSR_DCSR 0x7b0
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#define CSR_DPC 0x7b1
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#define CSR_DSCRATCH 0x7b2
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/* Performance Counters */
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#define CSR_MHPMCOUNTER3 0xb03
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#define CSR_MHPMCOUNTER4 0xb04
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#define CSR_MHPMCOUNTER5 0xb05
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#define CSR_MHPMCOUNTER6 0xb06
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#define CSR_MHPMCOUNTER7 0xb07
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#define CSR_MHPMCOUNTER8 0xb08
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#define CSR_MHPMCOUNTER9 0xb09
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#define CSR_MHPMCOUNTER10 0xb0a
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#define CSR_MHPMCOUNTER11 0xb0b
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#define CSR_MHPMCOUNTER12 0xb0c
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#define CSR_MHPMCOUNTER13 0xb0d
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#define CSR_MHPMCOUNTER14 0xb0e
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#define CSR_MHPMCOUNTER15 0xb0f
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#define CSR_MHPMCOUNTER16 0xb10
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#define CSR_MHPMCOUNTER17 0xb11
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#define CSR_MHPMCOUNTER18 0xb12
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#define CSR_MHPMCOUNTER19 0xb13
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#define CSR_MHPMCOUNTER20 0xb14
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#define CSR_MHPMCOUNTER21 0xb15
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#define CSR_MHPMCOUNTER22 0xb16
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#define CSR_MHPMCOUNTER23 0xb17
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#define CSR_MHPMCOUNTER24 0xb18
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#define CSR_MHPMCOUNTER25 0xb19
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#define CSR_MHPMCOUNTER26 0xb1a
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#define CSR_MHPMCOUNTER27 0xb1b
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#define CSR_MHPMCOUNTER28 0xb1c
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#define CSR_MHPMCOUNTER29 0xb1d
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#define CSR_MHPMCOUNTER30 0xb1e
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#define CSR_MHPMCOUNTER31 0xb1f
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#define CSR_MHPMEVENT3 0x323
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#define CSR_MHPMEVENT4 0x324
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#define CSR_MHPMEVENT5 0x325
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#define CSR_MHPMEVENT6 0x326
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#define CSR_MHPMEVENT7 0x327
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#define CSR_MHPMEVENT8 0x328
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#define CSR_MHPMEVENT9 0x329
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#define CSR_MHPMEVENT10 0x32a
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#define CSR_MHPMEVENT11 0x32b
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#define CSR_MHPMEVENT12 0x32c
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#define CSR_MHPMEVENT13 0x32d
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#define CSR_MHPMEVENT14 0x32e
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#define CSR_MHPMEVENT15 0x32f
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#define CSR_MHPMEVENT16 0x330
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#define CSR_MHPMEVENT17 0x331
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#define CSR_MHPMEVENT18 0x332
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#define CSR_MHPMEVENT19 0x333
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#define CSR_MHPMEVENT20 0x334
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#define CSR_MHPMEVENT21 0x335
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#define CSR_MHPMEVENT22 0x336
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#define CSR_MHPMEVENT23 0x337
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#define CSR_MHPMEVENT24 0x338
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#define CSR_MHPMEVENT25 0x339
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#define CSR_MHPMEVENT26 0x33a
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#define CSR_MHPMEVENT27 0x33b
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#define CSR_MHPMEVENT28 0x33c
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#define CSR_MHPMEVENT29 0x33d
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#define CSR_MHPMEVENT30 0x33e
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#define CSR_MHPMEVENT31 0x33f
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#define CSR_MHPMCOUNTER3H 0xb83
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#define CSR_MHPMCOUNTER4H 0xb84
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#define CSR_MHPMCOUNTER5H 0xb85
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#define CSR_MHPMCOUNTER6H 0xb86
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#define CSR_MHPMCOUNTER7H 0xb87
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#define CSR_MHPMCOUNTER8H 0xb88
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#define CSR_MHPMCOUNTER9H 0xb89
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#define CSR_MHPMCOUNTER10H 0xb8a
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#define CSR_MHPMCOUNTER11H 0xb8b
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#define CSR_MHPMCOUNTER12H 0xb8c
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#define CSR_MHPMCOUNTER13H 0xb8d
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#define CSR_MHPMCOUNTER14H 0xb8e
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#define CSR_MHPMCOUNTER15H 0xb8f
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#define CSR_MHPMCOUNTER16H 0xb90
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#define CSR_MHPMCOUNTER17H 0xb91
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#define CSR_MHPMCOUNTER18H 0xb92
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#define CSR_MHPMCOUNTER19H 0xb93
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#define CSR_MHPMCOUNTER20H 0xb94
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#define CSR_MHPMCOUNTER21H 0xb95
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#define CSR_MHPMCOUNTER22H 0xb96
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#define CSR_MHPMCOUNTER23H 0xb97
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#define CSR_MHPMCOUNTER24H 0xb98
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#define CSR_MHPMCOUNTER25H 0xb99
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#define CSR_MHPMCOUNTER26H 0xb9a
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#define CSR_MHPMCOUNTER27H 0xb9b
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#define CSR_MHPMCOUNTER28H 0xb9c
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#define CSR_MHPMCOUNTER29H 0xb9d
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#define CSR_MHPMCOUNTER30H 0xb9e
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#define CSR_MHPMCOUNTER31H 0xb9f
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/* mstatus CSR bits */
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#define MSTATUS_UIE 0x00000001
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#define MSTATUS_SIE 0x00000002
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#define MSTATUS_MIE 0x00000008
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#define MSTATUS_UPIE 0x00000010
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#define MSTATUS_SPIE 0x00000020
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#define MSTATUS_UBE 0x00000040
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#define MSTATUS_MPIE 0x00000080
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#define MSTATUS_SPP 0x00000100
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#define MSTATUS_MPP 0x00001800
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#define MSTATUS_FS 0x00006000
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#define MSTATUS_XS 0x00018000
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#define MSTATUS_MPRV 0x00020000
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#define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */
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#define MSTATUS_MXR 0x00080000
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#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
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#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
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#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
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#define MSTATUS_GVA 0x4000000000ULL
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#define MSTATUS_MPV 0x8000000000ULL
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#define MSTATUS64_UXL 0x0000000300000000ULL
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#define MSTATUS64_SXL 0x0000000C00000000ULL
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS64_SD 0x8000000000000000ULL
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#define MISA32_MXL 0xC0000000
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#define MISA64_MXL 0xC000000000000000ULL
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#define MXL_RV32 1
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#define MXL_RV64 2
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#define MXL_RV128 3
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#if defined(TARGET_RISCV32)
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#define MSTATUS_SD MSTATUS32_SD
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#define MISA_MXL MISA32_MXL
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#define MXL_VAL MXL_RV32
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#elif defined(TARGET_RISCV64)
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#define MSTATUS_SD MSTATUS64_SD
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#define MISA_MXL MISA64_MXL
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#define MXL_VAL MXL_RV64
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#endif
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/* sstatus CSR bits */
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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#define SSTATUS_SPIE 0x00000020
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#define SSTATUS_SPP 0x00000100
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
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#define SSTATUS_MXR 0x00080000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS64_SD 0x8000000000000000ULL
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#if defined(TARGET_RISCV32)
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#define SSTATUS_SD SSTATUS32_SD
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#elif defined(TARGET_RISCV64)
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#define SSTATUS_SD SSTATUS64_SD
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#endif
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/* hstatus CSR bits */
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#define HSTATUS_VSBE 0x00000020
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#define HSTATUS_GVA 0x00000040
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#define HSTATUS_SPV 0x00000080
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#define HSTATUS_SPVP 0x00000100
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#define HSTATUS_HU 0x00000200
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#define HSTATUS_VGEIN 0x0003F000
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#define HSTATUS_VTVM 0x00100000
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#define HSTATUS_VTSR 0x00400000
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#define HSTATUS_VSXL 0x300000000
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#define HSTATUS32_WPRI 0xFF8FF87E
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#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
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#if defined(TARGET_RISCV32)
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#define HSTATUS_WPRI HSTATUS32_WPRI
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#elif defined(TARGET_RISCV64)
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#define HSTATUS_WPRI HSTATUS64_WPRI
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#endif
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#define HCOUNTEREN_CY (1 << 0)
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#define HCOUNTEREN_TM (1 << 1)
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#define HCOUNTEREN_IR (1 << 2)
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#define HCOUNTEREN_HPM3 (1 << 3)
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/* Privilege modes */
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#define PRV_U 0
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#define PRV_S 1
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#define PRV_H 2 /* Reserved */
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#define PRV_M 3
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/* Virtulisation Register Fields */
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#define VIRT_ONOFF 1
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/* This is used to save state for when we take an exception. If this is set
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* that means that we want to force a HS level exception (no matter what the
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* delegation is set to). This will occur for things such as a second level
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* page table fault.
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*/
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#define FORCE_HS_EXCEP 2
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/* RV32 satp CSR field masks */
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#define SATP32_MODE 0x80000000
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#define SATP32_ASID 0x7fc00000
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#define SATP32_PPN 0x003fffff
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/* RV64 satp CSR field masks */
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#define SATP64_MODE 0xF000000000000000ULL
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#define SATP64_ASID 0x0FFFF00000000000ULL
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#define SATP64_PPN 0x00000FFFFFFFFFFFULL
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#if defined(TARGET_RISCV32)
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#define SATP_MODE SATP32_MODE
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#define SATP_ASID SATP32_ASID
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#define SATP_PPN SATP32_PPN
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#endif
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#if defined(TARGET_RISCV64)
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#define SATP_MODE SATP64_MODE
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#define SATP_ASID SATP64_ASID
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#define SATP_PPN SATP64_PPN
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#endif
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/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
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#define VM_1_09_MBARE 0
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#define VM_1_09_MBB 1
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#define VM_1_09_MBBID 2
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#define VM_1_09_SV32 8
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#define VM_1_09_SV39 9
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#define VM_1_09_SV48 10
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/* VM modes (satp.mode) privileged ISA 1.10 */
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#define VM_1_10_MBARE 0
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#define VM_1_10_SV32 1
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#define VM_1_10_SV39 8
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#define VM_1_10_SV48 9
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#define VM_1_10_SV57 10
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#define VM_1_10_SV64 11
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/* Page table entry (PTE) fields */
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#define PTE_V 0x001 /* Valid */
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#define PTE_R 0x002 /* Read */
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#define PTE_W 0x004 /* Write */
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#define PTE_X 0x008 /* Execute */
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#define PTE_U 0x010 /* User */
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#define PTE_G 0x020 /* Global */
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#define PTE_A 0x040 /* Accessed */
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#define PTE_D 0x080 /* Dirty */
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#define PTE_SOFT 0x300 /* Reserved for Software */
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/* Page table PPN shift amount */
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#define PTE_PPN_SHIFT 10
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/* Leaf page shift amount */
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#define PGSHIFT 12
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/* Default Reset Vector adress */
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#define DEFAULT_RSTVEC 0x1000
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/* Exception causes */
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typedef enum RISCVException {
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RISCV_EXCP_NONE = -1, /* sentinel value */
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RISCV_EXCP_INST_ADDR_MIS = 0x0,
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RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
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RISCV_EXCP_ILLEGAL_INST = 0x2,
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RISCV_EXCP_BREAKPOINT = 0x3,
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RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
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RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
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RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
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RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
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RISCV_EXCP_U_ECALL = 0x8,
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RISCV_EXCP_S_ECALL = 0x9,
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RISCV_EXCP_VS_ECALL = 0xa,
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RISCV_EXCP_M_ECALL = 0xb,
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RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
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RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
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RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
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RISCV_EXCP_SEMIHOST = 0x10,
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RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
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RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
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RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
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RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
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} RISCVException;
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#define RISCV_EXCP_INT_FLAG 0x80000000
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#define RISCV_EXCP_INT_MASK 0x7fffffff
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/* Interrupt causes */
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#define IRQ_U_SOFT 0
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#define IRQ_S_SOFT 1
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|
#define IRQ_VS_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_U_TIMER 4
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|
#define IRQ_S_TIMER 5
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|
#define IRQ_VS_TIMER 6
|
|
#define IRQ_M_TIMER 7
|
|
#define IRQ_U_EXT 8
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#define IRQ_S_EXT 9
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#define IRQ_VS_EXT 10
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|
#define IRQ_M_EXT 11
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|
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/* mip masks */
|
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#define MIP_USIP (1 << IRQ_U_SOFT)
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#define MIP_SSIP (1 << IRQ_S_SOFT)
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|
#define MIP_VSSIP (1 << IRQ_VS_SOFT)
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|
#define MIP_MSIP (1 << IRQ_M_SOFT)
|
|
#define MIP_UTIP (1 << IRQ_U_TIMER)
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|
#define MIP_STIP (1 << IRQ_S_TIMER)
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#define MIP_VSTIP (1 << IRQ_VS_TIMER)
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|
#define MIP_MTIP (1 << IRQ_M_TIMER)
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|
#define MIP_UEIP (1 << IRQ_U_EXT)
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|
#define MIP_SEIP (1 << IRQ_S_EXT)
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#define MIP_VSEIP (1 << IRQ_VS_EXT)
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|
#define MIP_MEIP (1 << IRQ_M_EXT)
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|
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/* sip masks */
|
|
#define SIP_SSIP MIP_SSIP
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|
#define SIP_STIP MIP_STIP
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|
#define SIP_SEIP MIP_SEIP
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|
|
/* MIE masks */
|
|
#define MIE_SEIE (1 << IRQ_S_EXT)
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|
#define MIE_UEIE (1 << IRQ_U_EXT)
|
|
#define MIE_STIE (1 << IRQ_S_TIMER)
|
|
#define MIE_UTIE (1 << IRQ_U_TIMER)
|
|
#define MIE_SSIE (1 << IRQ_S_SOFT)
|
|
#define MIE_USIE (1 << IRQ_U_SOFT)
|
|
#endif
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