qemu/target/riscv
Rajnesh Kanwal c5969a3a3c
target/riscv: Fix VS mode interrupts forwarding.
Currently riscv_cpu_local_irq_pending is used to find out pending
interrupt and VS mode interrupts are being shifted to represent
S mode interrupts in this function. So when the cause returned by
this function is passed to riscv_cpu_do_interrupt to actually
forward the interrupt, the VS mode forwarding check does not work
as intended and interrupt is actually forwarded to hypervisor. This
patch fixes this issue.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-03-16 17:03:51 -07:00
..
insn_trans
Makefile.objs
cpu-param.h
cpu.c RISC-V: Add a missing "," in riscv_excp_names 2020-03-05 12:01:43 -08:00
cpu.h target/riscv: Emulate TIME CSRs for privileged mode 2020-02-27 13:46:36 -08:00
cpu_bits.h target/riscv: Add the MSTATUS_MPV_ISSET helper macro 2020-02-27 13:46:33 -08:00
cpu_helper.c target/riscv: Fix VS mode interrupts forwarding. 2020-03-16 17:03:51 -07:00
cpu_user.h
csr.c target/riscv: Emulate TIME CSRs for privileged mode 2020-02-27 13:46:36 -08:00
fpu_helper.c
gdbstub.c
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
monitor.c
op_helper.c target/riscv: Correctly implement TSR trap 2020-03-16 17:03:13 -07:00
pmp.c
pmp.h
trace-events
translate.c target/riscv: Add the MSTATUS_MPV_ISSET helper macro 2020-02-27 13:46:33 -08:00