Anup Patel 31e6d70485 hw/riscv/spike: Allow more than one CPUs ... Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200427080644.168461-4-anup.patel@wdc.com Message-Id: <20200427080644.168461-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-04-29 13:16:38 -07:00
..
boot.c	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	2020-04-29 13:16:38 -07:00
Kconfig	riscv: virt: Use Goldfish RTC device	2020-02-10 12:01:38 -08:00
Makefile.objs	riscv: sifive: Implement a model for SiFive FU540 OTP	2019-09-17 08:42:49 -07:00
riscv_hart.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
riscv_htif.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
sifive_clint.c	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	2020-02-27 13:46:37 -08:00
sifive_e_prci.c	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_e.c	riscv: sifive_e: Support changing CPU type	2020-04-29 13:16:37 -07:00
sifive_gpio.c
sifive_plic.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_test.c
sifive_u_otp.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_u_prci.c	riscv: sifive: Implement PRCI model for FU540	2019-09-17 08:42:47 -07:00
sifive_u.c	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	2020-04-29 13:16:38 -07:00
sifive_uart.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
spike.c	hw/riscv/spike: Allow more than one CPUs	2020-04-29 13:16:38 -07:00
trace-events
virt.c	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	2020-04-29 13:16:38 -07:00