Joel Sing c13b169f1a

RISC-V: Clear load reservations on context switch and SC ...

This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.

Signed-off-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2019-06-25 22:37:04 -07:00

..

insn_trans

RISC-V: Clear load reservations on context switch and SC

2019-06-25 22:37:04 -07:00

cpu_bits.h

target/riscv: Add the mcountinhibit CSR

2019-06-25 03:05:40 -07:00

cpu_helper.c

RISC-V: Clear load reservations on context switch and SC

2019-06-25 22:37:04 -07:00

cpu_user.h

Supply missing header guards

2019-06-12 13:20:21 +02:00

cpu-param.h

tcg: Split out target/arch/cpu-param.h

2019-06-10 07:03:34 -07:00

cpu.c

RISC-V: Clear load reservations on context switch and SC

2019-06-25 22:37:04 -07:00

cpu.h

RISC-V: Add support for the Zicsr extension

2019-06-25 22:32:42 -07:00

csr.c

RISC-V: Add support for the Zicsr extension

2019-06-25 22:32:42 -07:00

fpu_helper.c

RISC-V: Use riscv prefix consistently on cpu helpers

2019-02-11 15:56:21 -08:00

gdbstub.c

Include qemu-common.h exactly where needed

2019-06-12 13:20:20 +02:00

helper.h

…

insn16-32.decode

target/riscv: Split RVC32 and RVC64 insns into separate files

2019-05-24 12:09:22 -07:00

insn16-64.decode

target/riscv: Add checks for several RVC reserved operands

2019-05-24 12:09:25 -07:00

insn16.decode

target/riscv: Add checks for several RVC reserved operands

2019-05-24 12:09:25 -07:00

insn32-64.decode

target/riscv: Convert RV64D insns to decodetree

2019-03-13 10:34:06 +01:00

insn32.decode

target/riscv: Name the argument sets for all of insn32 formats

2019-05-24 12:09:22 -07:00

instmap.h

Supply missing header guards

2019-06-12 13:20:21 +02:00

Makefile.objs

target/riscv: Split RVC32 and RVC64 insns into separate files

2019-05-24 12:09:22 -07:00

op_helper.c

target/riscv: Use env_cpu, env_archcpu

2019-06-10 07:03:42 -07:00

pmp.c

RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off

2019-06-23 23:44:42 -07:00

pmp.h

RISC-V: Check for the effective memory privilege mode during PMP checks

2019-06-23 23:44:41 -07:00

trace-events

RISC-V: Convert trap debugging to trace events

2019-03-19 05:14:40 -07:00

translate.c

RISC-V: Add support for the Zifencei extension

2019-06-25 22:31:21 -07:00