30b2f8709d
Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
/*
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* Copyright (c) 2018, Impinj, Inc.
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*
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* i.MX7 GPR IP block emulation code
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* Bare minimum emulation code needed to support being able to shut
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* down linux guest gracefully.
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*/
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#include "qemu/osdep.h"
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#include "hw/misc/imx7_gpr.h"
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#include "qemu/log.h"
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#include "sysemu/sysemu.h"
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#include "trace.h"
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enum IMX7GPRRegisters {
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IOMUXC_GPR0 = 0x00,
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IOMUXC_GPR1 = 0x04,
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IOMUXC_GPR2 = 0x08,
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IOMUXC_GPR3 = 0x0c,
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IOMUXC_GPR4 = 0x10,
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IOMUXC_GPR5 = 0x14,
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IOMUXC_GPR6 = 0x18,
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IOMUXC_GPR7 = 0x1c,
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IOMUXC_GPR8 = 0x20,
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IOMUXC_GPR9 = 0x24,
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IOMUXC_GPR10 = 0x28,
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IOMUXC_GPR11 = 0x2c,
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IOMUXC_GPR12 = 0x30,
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IOMUXC_GPR13 = 0x34,
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IOMUXC_GPR14 = 0x38,
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IOMUXC_GPR15 = 0x3c,
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IOMUXC_GPR16 = 0x40,
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IOMUXC_GPR17 = 0x44,
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IOMUXC_GPR18 = 0x48,
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IOMUXC_GPR19 = 0x4c,
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IOMUXC_GPR20 = 0x50,
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IOMUXC_GPR21 = 0x54,
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IOMUXC_GPR22 = 0x58,
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};
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#define IMX7D_GPR1_IRQ_MASK BIT(12)
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#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK BIT(13)
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#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK BIT(14)
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#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)
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#define IMX7D_GPR1_ENET1_CLK_DIR_MASK BIT(17)
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#define IMX7D_GPR1_ENET2_CLK_DIR_MASK BIT(18)
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#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)
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#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI BIT(4)
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#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5)
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#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31)
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static uint64_t imx7_gpr_read(void *opaque, hwaddr offset, unsigned size)
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{
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trace_imx7_gpr_read(offset);
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if (offset == IOMUXC_GPR22) {
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return IMX7D_GPR22_PCIE_PHY_PLL_LOCKED;
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}
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return 0;
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}
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static void imx7_gpr_write(void *opaque, hwaddr offset,
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uint64_t v, unsigned size)
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{
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trace_imx7_gpr_write(offset, v);
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}
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static const struct MemoryRegionOps imx7_gpr_ops = {
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.read = imx7_gpr_read,
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.write = imx7_gpr_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the
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* real device but in practice there is no reason for a guest
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* to access this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void imx7_gpr_init(Object *obj)
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{
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SysBusDevice *sd = SYS_BUS_DEVICE(obj);
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IMX7GPRState *s = IMX7_GPR(obj);
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memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s,
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TYPE_IMX7_GPR, 64 * 1024);
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sysbus_init_mmio(sd, &s->mmio);
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}
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static void imx7_gpr_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "i.MX7 General Purpose Registers Module";
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}
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static const TypeInfo imx7_gpr_info = {
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.name = TYPE_IMX7_GPR,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMX7GPRState),
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.instance_init = imx7_gpr_init,
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.class_init = imx7_gpr_class_init,
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};
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static void imx7_gpr_register_type(void)
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{
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type_register_static(&imx7_gpr_info);
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}
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type_init(imx7_gpr_register_type)
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