Frank Chang 308ee80578 target/riscv: rvv-1.0: allow load element with sign-extended ... For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-35-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-12-20 14:51:36 +10:00
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trans_privileged.c.inc	target/riscv: Remove exit_tb and lookup_and_goto_ptr	2021-10-15 16:39:14 -07:00
trans_rva.c.inc	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions	2021-10-28 14:39:23 +10:00
trans_rvb.c.inc	target/riscv: Use gen_shift*_per_ol for RVB, RVI	2021-10-22 23:35:47 +10:00
trans_rvd.c.inc	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions	2021-10-28 14:39:23 +10:00
trans_rvf.c.inc	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions	2021-10-28 14:39:23 +10:00
trans_rvh.c.inc	target/riscv: Tidy trans_rvh.c.inc	2021-09-01 11:59:12 +10:00
trans_rvi.c.inc	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions	2021-10-28 14:39:23 +10:00
trans_rvm.c.inc	target/riscv: Use gen_arith_per_ol for RVM	2021-10-22 23:35:43 +10:00
trans_rvv.c.inc	target/riscv: rvv-1.0: allow load element with sign-extended	2021-12-20 14:51:36 +10:00
trans_rvzfh.c.inc	target/riscv: zfh: implement zfhmin extension	2021-12-20 14:51:36 +10:00