d44971e725
Delay generating the exception until after we know the
insn length, and record that length in env->error_code.
Fixes: 8ec7e3c53d ("target/mips: Use an exception for semihosting")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1126
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
1124 lines
30 KiB
C++
1124 lines
30 KiB
C++
/*
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* MIPS16 extension (Code Compaction) ASE translation routines
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2006 Marius Groeger (FPU operations)
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* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
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* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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/* MIPS16 major opcodes */
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enum {
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M16_OPC_ADDIUSP = 0x00,
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M16_OPC_ADDIUPC = 0x01,
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M16_OPC_B = 0x02,
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M16_OPC_JAL = 0x03,
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M16_OPC_BEQZ = 0x04,
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M16_OPC_BNEQZ = 0x05,
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M16_OPC_SHIFT = 0x06,
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M16_OPC_LD = 0x07,
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M16_OPC_RRIA = 0x08,
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M16_OPC_ADDIU8 = 0x09,
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M16_OPC_SLTI = 0x0a,
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M16_OPC_SLTIU = 0x0b,
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M16_OPC_I8 = 0x0c,
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M16_OPC_LI = 0x0d,
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M16_OPC_CMPI = 0x0e,
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M16_OPC_SD = 0x0f,
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M16_OPC_LB = 0x10,
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M16_OPC_LH = 0x11,
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M16_OPC_LWSP = 0x12,
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M16_OPC_LW = 0x13,
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M16_OPC_LBU = 0x14,
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M16_OPC_LHU = 0x15,
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M16_OPC_LWPC = 0x16,
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M16_OPC_LWU = 0x17,
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M16_OPC_SB = 0x18,
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M16_OPC_SH = 0x19,
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M16_OPC_SWSP = 0x1a,
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M16_OPC_SW = 0x1b,
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M16_OPC_RRR = 0x1c,
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M16_OPC_RR = 0x1d,
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M16_OPC_EXTEND = 0x1e,
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M16_OPC_I64 = 0x1f
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};
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/* I8 funct field */
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enum {
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I8_BTEQZ = 0x0,
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I8_BTNEZ = 0x1,
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I8_SWRASP = 0x2,
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I8_ADJSP = 0x3,
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I8_SVRS = 0x4,
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I8_MOV32R = 0x5,
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I8_MOVR32 = 0x7
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};
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/* RRR f field */
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enum {
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RRR_DADDU = 0x0,
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RRR_ADDU = 0x1,
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RRR_DSUBU = 0x2,
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RRR_SUBU = 0x3
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};
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/* RR funct field */
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enum {
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RR_JR = 0x00,
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RR_SDBBP = 0x01,
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RR_SLT = 0x02,
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RR_SLTU = 0x03,
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RR_SLLV = 0x04,
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RR_BREAK = 0x05,
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RR_SRLV = 0x06,
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RR_SRAV = 0x07,
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RR_DSRL = 0x08,
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RR_CMP = 0x0a,
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RR_NEG = 0x0b,
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RR_AND = 0x0c,
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RR_OR = 0x0d,
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RR_XOR = 0x0e,
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RR_NOT = 0x0f,
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RR_MFHI = 0x10,
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RR_CNVT = 0x11,
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RR_MFLO = 0x12,
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RR_DSRA = 0x13,
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RR_DSLLV = 0x14,
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RR_DSRLV = 0x16,
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RR_DSRAV = 0x17,
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RR_MULT = 0x18,
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RR_MULTU = 0x19,
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RR_DIV = 0x1a,
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RR_DIVU = 0x1b,
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RR_DMULT = 0x1c,
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RR_DMULTU = 0x1d,
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RR_DDIV = 0x1e,
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RR_DDIVU = 0x1f
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};
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/* I64 funct field */
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enum {
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I64_LDSP = 0x0,
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I64_SDSP = 0x1,
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I64_SDRASP = 0x2,
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I64_DADJSP = 0x3,
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I64_LDPC = 0x4,
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I64_DADDIU5 = 0x5,
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I64_DADDIUPC = 0x6,
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I64_DADDIUSP = 0x7
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};
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/* RR ry field for CNVT */
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enum {
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RR_RY_CNVT_ZEB = 0x0,
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RR_RY_CNVT_ZEH = 0x1,
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RR_RY_CNVT_ZEW = 0x2,
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RR_RY_CNVT_SEB = 0x4,
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RR_RY_CNVT_SEH = 0x5,
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RR_RY_CNVT_SEW = 0x6,
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};
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static int xlat(int r)
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{
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static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
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return map[r];
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}
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static void gen_mips16_save(DisasContext *ctx,
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int xsregs, int aregs,
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int do_ra, int do_s0, int do_s1,
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int framesize)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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int args, astatic;
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switch (aregs) {
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case 0:
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case 1:
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case 2:
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case 3:
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case 11:
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args = 0;
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break;
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case 4:
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case 5:
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case 6:
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case 7:
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args = 1;
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break;
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case 8:
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case 9:
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case 10:
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args = 2;
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break;
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case 12:
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case 13:
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args = 3;
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break;
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case 14:
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args = 4;
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break;
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default:
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gen_reserved_instruction(ctx);
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return;
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}
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switch (args) {
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case 4:
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gen_base_offset_addr(ctx, t0, 29, 12);
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gen_load_gpr(t1, 7);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
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/* Fall through */
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case 3:
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gen_base_offset_addr(ctx, t0, 29, 8);
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gen_load_gpr(t1, 6);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
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/* Fall through */
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case 2:
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gen_base_offset_addr(ctx, t0, 29, 4);
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gen_load_gpr(t1, 5);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
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/* Fall through */
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case 1:
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gen_base_offset_addr(ctx, t0, 29, 0);
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gen_load_gpr(t1, 4);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
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}
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gen_load_gpr(t0, 29);
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#define DECR_AND_STORE(reg) do { \
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tcg_gen_movi_tl(t2, -4); \
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gen_op_addr_add(ctx, t0, t0, t2); \
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gen_load_gpr(t1, reg); \
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \
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} while (0)
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if (do_ra) {
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DECR_AND_STORE(31);
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}
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switch (xsregs) {
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case 7:
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DECR_AND_STORE(30);
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/* Fall through */
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case 6:
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DECR_AND_STORE(23);
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/* Fall through */
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case 5:
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DECR_AND_STORE(22);
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/* Fall through */
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case 4:
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DECR_AND_STORE(21);
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/* Fall through */
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case 3:
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DECR_AND_STORE(20);
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/* Fall through */
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case 2:
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DECR_AND_STORE(19);
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/* Fall through */
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case 1:
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DECR_AND_STORE(18);
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}
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if (do_s1) {
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DECR_AND_STORE(17);
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}
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if (do_s0) {
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DECR_AND_STORE(16);
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}
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switch (aregs) {
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case 0:
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case 4:
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case 8:
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case 12:
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case 14:
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astatic = 0;
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break;
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case 1:
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case 5:
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case 9:
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case 13:
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astatic = 1;
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break;
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case 2:
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case 6:
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case 10:
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astatic = 2;
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break;
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case 3:
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case 7:
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astatic = 3;
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break;
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case 11:
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astatic = 4;
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break;
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default:
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gen_reserved_instruction(ctx);
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return;
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}
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if (astatic > 0) {
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DECR_AND_STORE(7);
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if (astatic > 1) {
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DECR_AND_STORE(6);
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if (astatic > 2) {
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DECR_AND_STORE(5);
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if (astatic > 3) {
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DECR_AND_STORE(4);
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}
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}
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}
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}
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#undef DECR_AND_STORE
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tcg_gen_movi_tl(t2, -framesize);
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gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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tcg_temp_free(t2);
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}
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static void gen_mips16_restore(DisasContext *ctx,
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int xsregs, int aregs,
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int do_ra, int do_s0, int do_s1,
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int framesize)
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{
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int astatic;
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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tcg_gen_movi_tl(t2, framesize);
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gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
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#define DECR_AND_LOAD(reg) do { \
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tcg_gen_movi_tl(t2, -4); \
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gen_op_addr_add(ctx, t0, t0, t2); \
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \
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gen_store_gpr(t1, reg); \
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} while (0)
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if (do_ra) {
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DECR_AND_LOAD(31);
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}
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switch (xsregs) {
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case 7:
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DECR_AND_LOAD(30);
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/* Fall through */
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case 6:
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DECR_AND_LOAD(23);
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/* Fall through */
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case 5:
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DECR_AND_LOAD(22);
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/* Fall through */
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case 4:
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DECR_AND_LOAD(21);
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/* Fall through */
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case 3:
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DECR_AND_LOAD(20);
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/* Fall through */
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case 2:
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DECR_AND_LOAD(19);
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/* Fall through */
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case 1:
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DECR_AND_LOAD(18);
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}
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if (do_s1) {
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DECR_AND_LOAD(17);
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}
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if (do_s0) {
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DECR_AND_LOAD(16);
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}
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switch (aregs) {
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case 0:
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case 4:
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case 8:
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case 12:
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case 14:
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astatic = 0;
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break;
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case 1:
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case 5:
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case 9:
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case 13:
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astatic = 1;
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break;
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case 2:
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case 6:
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case 10:
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astatic = 2;
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break;
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case 3:
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case 7:
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astatic = 3;
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break;
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case 11:
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astatic = 4;
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break;
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default:
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gen_reserved_instruction(ctx);
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return;
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}
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if (astatic > 0) {
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DECR_AND_LOAD(7);
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if (astatic > 1) {
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DECR_AND_LOAD(6);
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if (astatic > 2) {
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DECR_AND_LOAD(5);
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if (astatic > 3) {
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DECR_AND_LOAD(4);
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}
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}
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}
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}
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#undef DECR_AND_LOAD
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tcg_gen_movi_tl(t2, framesize);
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gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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tcg_temp_free(t2);
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}
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|
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#if defined(TARGET_MIPS64)
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static void decode_i64_mips16(DisasContext *ctx,
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int ry, int funct, int16_t offset,
|
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int extended)
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{
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switch (funct) {
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case I64_LDSP:
|
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check_insn(ctx, ISA_MIPS3);
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check_mips_64(ctx);
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offset = extended ? offset : offset << 3;
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gen_ld(ctx, OPC_LD, ry, 29, offset);
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break;
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case I64_SDSP:
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check_insn(ctx, ISA_MIPS3);
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check_mips_64(ctx);
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offset = extended ? offset : offset << 3;
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gen_st(ctx, OPC_SD, ry, 29, offset);
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break;
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case I64_SDRASP:
|
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check_insn(ctx, ISA_MIPS3);
|
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check_mips_64(ctx);
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offset = extended ? offset : (ctx->opcode & 0xff) << 3;
|
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gen_st(ctx, OPC_SD, 31, 29, offset);
|
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break;
|
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case I64_DADJSP:
|
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check_insn(ctx, ISA_MIPS3);
|
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check_mips_64(ctx);
|
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offset = extended ? offset : ((int8_t)ctx->opcode) << 3;
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gen_arith_imm(ctx, OPC_DADDIU, 29, 29, offset);
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break;
|
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case I64_LDPC:
|
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check_insn(ctx, ISA_MIPS3);
|
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check_mips_64(ctx);
|
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if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
|
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gen_reserved_instruction(ctx);
|
|
} else {
|
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offset = extended ? offset : offset << 3;
|
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gen_ld(ctx, OPC_LDPC, ry, 0, offset);
|
|
}
|
|
break;
|
|
case I64_DADDIU5:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
offset = extended ? offset : ((int8_t)(offset << 3)) >> 3;
|
|
gen_arith_imm(ctx, OPC_DADDIU, ry, ry, offset);
|
|
break;
|
|
case I64_DADDIUPC:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
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offset = extended ? offset : offset << 2;
|
|
gen_addiupc(ctx, ry, offset, 1, extended);
|
|
break;
|
|
case I64_DADDIUSP:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
offset = extended ? offset : offset << 2;
|
|
gen_arith_imm(ctx, OPC_DADDIU, ry, 29, offset);
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
|
|
{
|
|
int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
|
|
int op, rx, ry, funct, sa;
|
|
int16_t imm, offset;
|
|
|
|
ctx->opcode = (ctx->opcode << 16) | extend;
|
|
op = (ctx->opcode >> 11) & 0x1f;
|
|
sa = (ctx->opcode >> 22) & 0x1f;
|
|
funct = (ctx->opcode >> 8) & 0x7;
|
|
rx = xlat((ctx->opcode >> 8) & 0x7);
|
|
ry = xlat((ctx->opcode >> 5) & 0x7);
|
|
offset = imm = (int16_t) (((ctx->opcode >> 16) & 0x1f) << 11
|
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| ((ctx->opcode >> 21) & 0x3f) << 5
|
|
| (ctx->opcode & 0x1f));
|
|
|
|
/*
|
|
* The extended opcodes cleverly reuse the opcodes from their 16-bit
|
|
* counterparts.
|
|
*/
|
|
switch (op) {
|
|
case M16_OPC_ADDIUSP:
|
|
gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
|
|
break;
|
|
case M16_OPC_ADDIUPC:
|
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gen_addiupc(ctx, rx, imm, 0, 1);
|
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break;
|
|
case M16_OPC_B:
|
|
gen_compute_branch(ctx, OPC_BEQ, 4, 0, 0, offset << 1, 0);
|
|
/* No delay slot, so just process as a normal instruction */
|
|
break;
|
|
case M16_OPC_BEQZ:
|
|
gen_compute_branch(ctx, OPC_BEQ, 4, rx, 0, offset << 1, 0);
|
|
/* No delay slot, so just process as a normal instruction */
|
|
break;
|
|
case M16_OPC_BNEQZ:
|
|
gen_compute_branch(ctx, OPC_BNE, 4, rx, 0, offset << 1, 0);
|
|
/* No delay slot, so just process as a normal instruction */
|
|
break;
|
|
case M16_OPC_SHIFT:
|
|
switch (ctx->opcode & 0x3) {
|
|
case 0x0:
|
|
gen_shift_imm(ctx, OPC_SLL, rx, ry, sa);
|
|
break;
|
|
case 0x1:
|
|
#if defined(TARGET_MIPS64)
|
|
check_mips_64(ctx);
|
|
gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
|
|
#else
|
|
gen_reserved_instruction(ctx);
|
|
#endif
|
|
break;
|
|
case 0x2:
|
|
gen_shift_imm(ctx, OPC_SRL, rx, ry, sa);
|
|
break;
|
|
case 0x3:
|
|
gen_shift_imm(ctx, OPC_SRA, rx, ry, sa);
|
|
break;
|
|
}
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case M16_OPC_LD:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_ld(ctx, OPC_LD, ry, rx, offset);
|
|
break;
|
|
#endif
|
|
case M16_OPC_RRIA:
|
|
imm = ctx->opcode & 0xf;
|
|
imm = imm | ((ctx->opcode >> 20) & 0x7f) << 4;
|
|
imm = imm | ((ctx->opcode >> 16) & 0xf) << 11;
|
|
imm = (int16_t) (imm << 1) >> 1;
|
|
if ((ctx->opcode >> 4) & 0x1) {
|
|
#if defined(TARGET_MIPS64)
|
|
check_mips_64(ctx);
|
|
gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
|
|
#else
|
|
gen_reserved_instruction(ctx);
|
|
#endif
|
|
} else {
|
|
gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
|
|
}
|
|
break;
|
|
case M16_OPC_ADDIU8:
|
|
gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm);
|
|
break;
|
|
case M16_OPC_SLTI:
|
|
gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm);
|
|
break;
|
|
case M16_OPC_SLTIU:
|
|
gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm);
|
|
break;
|
|
case M16_OPC_I8:
|
|
switch (funct) {
|
|
case I8_BTEQZ:
|
|
gen_compute_branch(ctx, OPC_BEQ, 4, 24, 0, offset << 1, 0);
|
|
break;
|
|
case I8_BTNEZ:
|
|
gen_compute_branch(ctx, OPC_BNE, 4, 24, 0, offset << 1, 0);
|
|
break;
|
|
case I8_SWRASP:
|
|
gen_st(ctx, OPC_SW, 31, 29, imm);
|
|
break;
|
|
case I8_ADJSP:
|
|
gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm);
|
|
break;
|
|
case I8_SVRS:
|
|
check_insn(ctx, ISA_MIPS_R1);
|
|
{
|
|
int xsregs = (ctx->opcode >> 24) & 0x7;
|
|
int aregs = (ctx->opcode >> 16) & 0xf;
|
|
int do_ra = (ctx->opcode >> 6) & 0x1;
|
|
int do_s0 = (ctx->opcode >> 5) & 0x1;
|
|
int do_s1 = (ctx->opcode >> 4) & 0x1;
|
|
int framesize = (((ctx->opcode >> 20) & 0xf) << 4
|
|
| (ctx->opcode & 0xf)) << 3;
|
|
|
|
if (ctx->opcode & (1 << 7)) {
|
|
gen_mips16_save(ctx, xsregs, aregs,
|
|
do_ra, do_s0, do_s1,
|
|
framesize);
|
|
} else {
|
|
gen_mips16_restore(ctx, xsregs, aregs,
|
|
do_ra, do_s0, do_s1,
|
|
framesize);
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
gen_reserved_instruction(ctx);
|
|
break;
|
|
}
|
|
break;
|
|
case M16_OPC_LI:
|
|
tcg_gen_movi_tl(cpu_gpr[rx], (uint16_t) imm);
|
|
break;
|
|
case M16_OPC_CMPI:
|
|
tcg_gen_xori_tl(cpu_gpr[24], cpu_gpr[rx], (uint16_t) imm);
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case M16_OPC_SD:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_st(ctx, OPC_SD, ry, rx, offset);
|
|
break;
|
|
#endif
|
|
case M16_OPC_LB:
|
|
gen_ld(ctx, OPC_LB, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_LH:
|
|
gen_ld(ctx, OPC_LH, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_LWSP:
|
|
gen_ld(ctx, OPC_LW, rx, 29, offset);
|
|
break;
|
|
case M16_OPC_LW:
|
|
gen_ld(ctx, OPC_LW, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_LBU:
|
|
gen_ld(ctx, OPC_LBU, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_LHU:
|
|
gen_ld(ctx, OPC_LHU, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_LWPC:
|
|
gen_ld(ctx, OPC_LWPC, rx, 0, offset);
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case M16_OPC_LWU:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_ld(ctx, OPC_LWU, ry, rx, offset);
|
|
break;
|
|
#endif
|
|
case M16_OPC_SB:
|
|
gen_st(ctx, OPC_SB, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_SH:
|
|
gen_st(ctx, OPC_SH, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_SWSP:
|
|
gen_st(ctx, OPC_SW, rx, 29, offset);
|
|
break;
|
|
case M16_OPC_SW:
|
|
gen_st(ctx, OPC_SW, ry, rx, offset);
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case M16_OPC_I64:
|
|
decode_i64_mips16(ctx, ry, funct, offset, 1);
|
|
break;
|
|
#endif
|
|
default:
|
|
gen_reserved_instruction(ctx);
|
|
break;
|
|
}
|
|
|
|
return 4;
|
|
}
|
|
|
|
static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
|
|
{
|
|
int rx, ry;
|
|
int sa;
|
|
int op, cnvt_op, op1, offset;
|
|
int funct;
|
|
int n_bytes;
|
|
|
|
op = (ctx->opcode >> 11) & 0x1f;
|
|
sa = (ctx->opcode >> 2) & 0x7;
|
|
sa = sa == 0 ? 8 : sa;
|
|
rx = xlat((ctx->opcode >> 8) & 0x7);
|
|
cnvt_op = (ctx->opcode >> 5) & 0x7;
|
|
ry = xlat((ctx->opcode >> 5) & 0x7);
|
|
op1 = offset = ctx->opcode & 0x1f;
|
|
|
|
n_bytes = 2;
|
|
|
|
switch (op) {
|
|
case M16_OPC_ADDIUSP:
|
|
{
|
|
int16_t imm = ((uint8_t) ctx->opcode) << 2;
|
|
|
|
gen_arith_imm(ctx, OPC_ADDIU, rx, 29, imm);
|
|
}
|
|
break;
|
|
case M16_OPC_ADDIUPC:
|
|
gen_addiupc(ctx, rx, ((uint8_t) ctx->opcode) << 2, 0, 0);
|
|
break;
|
|
case M16_OPC_B:
|
|
offset = (ctx->opcode & 0x7ff) << 1;
|
|
offset = (int16_t)(offset << 4) >> 4;
|
|
gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, offset, 0);
|
|
/* No delay slot, so just process as a normal instruction */
|
|
break;
|
|
case M16_OPC_JAL:
|
|
offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
|
|
offset = (((ctx->opcode & 0x1f) << 21)
|
|
| ((ctx->opcode >> 5) & 0x1f) << 16
|
|
| offset) << 2;
|
|
op = ((ctx->opcode >> 10) & 0x1) ? OPC_JALX : OPC_JAL;
|
|
gen_compute_branch(ctx, op, 4, rx, ry, offset, 2);
|
|
n_bytes = 4;
|
|
break;
|
|
case M16_OPC_BEQZ:
|
|
gen_compute_branch(ctx, OPC_BEQ, 2, rx, 0,
|
|
((int8_t)ctx->opcode) << 1, 0);
|
|
/* No delay slot, so just process as a normal instruction */
|
|
break;
|
|
case M16_OPC_BNEQZ:
|
|
gen_compute_branch(ctx, OPC_BNE, 2, rx, 0,
|
|
((int8_t)ctx->opcode) << 1, 0);
|
|
/* No delay slot, so just process as a normal instruction */
|
|
break;
|
|
case M16_OPC_SHIFT:
|
|
switch (ctx->opcode & 0x3) {
|
|
case 0x0:
|
|
gen_shift_imm(ctx, OPC_SLL, rx, ry, sa);
|
|
break;
|
|
case 0x1:
|
|
#if defined(TARGET_MIPS64)
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
|
|
#else
|
|
gen_reserved_instruction(ctx);
|
|
#endif
|
|
break;
|
|
case 0x2:
|
|
gen_shift_imm(ctx, OPC_SRL, rx, ry, sa);
|
|
break;
|
|
case 0x3:
|
|
gen_shift_imm(ctx, OPC_SRA, rx, ry, sa);
|
|
break;
|
|
}
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case M16_OPC_LD:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_ld(ctx, OPC_LD, ry, rx, offset << 3);
|
|
break;
|
|
#endif
|
|
case M16_OPC_RRIA:
|
|
{
|
|
int16_t imm = (int8_t)((ctx->opcode & 0xf) << 4) >> 4;
|
|
|
|
if ((ctx->opcode >> 4) & 1) {
|
|
#if defined(TARGET_MIPS64)
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
|
|
#else
|
|
gen_reserved_instruction(ctx);
|
|
#endif
|
|
} else {
|
|
gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
|
|
}
|
|
}
|
|
break;
|
|
case M16_OPC_ADDIU8:
|
|
{
|
|
int16_t imm = (int8_t) ctx->opcode;
|
|
|
|
gen_arith_imm(ctx, OPC_ADDIU, rx, rx, imm);
|
|
}
|
|
break;
|
|
case M16_OPC_SLTI:
|
|
{
|
|
int16_t imm = (uint8_t) ctx->opcode;
|
|
gen_slt_imm(ctx, OPC_SLTI, 24, rx, imm);
|
|
}
|
|
break;
|
|
case M16_OPC_SLTIU:
|
|
{
|
|
int16_t imm = (uint8_t) ctx->opcode;
|
|
gen_slt_imm(ctx, OPC_SLTIU, 24, rx, imm);
|
|
}
|
|
break;
|
|
case M16_OPC_I8:
|
|
{
|
|
int reg32;
|
|
|
|
funct = (ctx->opcode >> 8) & 0x7;
|
|
switch (funct) {
|
|
case I8_BTEQZ:
|
|
gen_compute_branch(ctx, OPC_BEQ, 2, 24, 0,
|
|
((int8_t)ctx->opcode) << 1, 0);
|
|
break;
|
|
case I8_BTNEZ:
|
|
gen_compute_branch(ctx, OPC_BNE, 2, 24, 0,
|
|
((int8_t)ctx->opcode) << 1, 0);
|
|
break;
|
|
case I8_SWRASP:
|
|
gen_st(ctx, OPC_SW, 31, 29, (ctx->opcode & 0xff) << 2);
|
|
break;
|
|
case I8_ADJSP:
|
|
gen_arith_imm(ctx, OPC_ADDIU, 29, 29,
|
|
((int8_t)ctx->opcode) << 3);
|
|
break;
|
|
case I8_SVRS:
|
|
check_insn(ctx, ISA_MIPS_R1);
|
|
{
|
|
int do_ra = ctx->opcode & (1 << 6);
|
|
int do_s0 = ctx->opcode & (1 << 5);
|
|
int do_s1 = ctx->opcode & (1 << 4);
|
|
int framesize = ctx->opcode & 0xf;
|
|
|
|
if (framesize == 0) {
|
|
framesize = 128;
|
|
} else {
|
|
framesize = framesize << 3;
|
|
}
|
|
|
|
if (ctx->opcode & (1 << 7)) {
|
|
gen_mips16_save(ctx, 0, 0,
|
|
do_ra, do_s0, do_s1, framesize);
|
|
} else {
|
|
gen_mips16_restore(ctx, 0, 0,
|
|
do_ra, do_s0, do_s1, framesize);
|
|
}
|
|
}
|
|
break;
|
|
case I8_MOV32R:
|
|
{
|
|
int rz = xlat(ctx->opcode & 0x7);
|
|
|
|
reg32 = (((ctx->opcode >> 3) & 0x3) << 3) |
|
|
((ctx->opcode >> 5) & 0x7);
|
|
gen_arith(ctx, OPC_ADDU, reg32, rz, 0);
|
|
}
|
|
break;
|
|
case I8_MOVR32:
|
|
reg32 = ctx->opcode & 0x1f;
|
|
gen_arith(ctx, OPC_ADDU, ry, reg32, 0);
|
|
break;
|
|
default:
|
|
gen_reserved_instruction(ctx);
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case M16_OPC_LI:
|
|
{
|
|
int16_t imm = (uint8_t) ctx->opcode;
|
|
|
|
gen_arith_imm(ctx, OPC_ADDIU, rx, 0, imm);
|
|
}
|
|
break;
|
|
case M16_OPC_CMPI:
|
|
{
|
|
int16_t imm = (uint8_t) ctx->opcode;
|
|
gen_logic_imm(ctx, OPC_XORI, 24, rx, imm);
|
|
}
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case M16_OPC_SD:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_st(ctx, OPC_SD, ry, rx, offset << 3);
|
|
break;
|
|
#endif
|
|
case M16_OPC_LB:
|
|
gen_ld(ctx, OPC_LB, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_LH:
|
|
gen_ld(ctx, OPC_LH, ry, rx, offset << 1);
|
|
break;
|
|
case M16_OPC_LWSP:
|
|
gen_ld(ctx, OPC_LW, rx, 29, ((uint8_t)ctx->opcode) << 2);
|
|
break;
|
|
case M16_OPC_LW:
|
|
gen_ld(ctx, OPC_LW, ry, rx, offset << 2);
|
|
break;
|
|
case M16_OPC_LBU:
|
|
gen_ld(ctx, OPC_LBU, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_LHU:
|
|
gen_ld(ctx, OPC_LHU, ry, rx, offset << 1);
|
|
break;
|
|
case M16_OPC_LWPC:
|
|
gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2);
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case M16_OPC_LWU:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_ld(ctx, OPC_LWU, ry, rx, offset << 2);
|
|
break;
|
|
#endif
|
|
case M16_OPC_SB:
|
|
gen_st(ctx, OPC_SB, ry, rx, offset);
|
|
break;
|
|
case M16_OPC_SH:
|
|
gen_st(ctx, OPC_SH, ry, rx, offset << 1);
|
|
break;
|
|
case M16_OPC_SWSP:
|
|
gen_st(ctx, OPC_SW, rx, 29, ((uint8_t)ctx->opcode) << 2);
|
|
break;
|
|
case M16_OPC_SW:
|
|
gen_st(ctx, OPC_SW, ry, rx, offset << 2);
|
|
break;
|
|
case M16_OPC_RRR:
|
|
{
|
|
int rz = xlat((ctx->opcode >> 2) & 0x7);
|
|
int mips32_op;
|
|
|
|
switch (ctx->opcode & 0x3) {
|
|
case RRR_ADDU:
|
|
mips32_op = OPC_ADDU;
|
|
break;
|
|
case RRR_SUBU:
|
|
mips32_op = OPC_SUBU;
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case RRR_DADDU:
|
|
mips32_op = OPC_DADDU;
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
break;
|
|
case RRR_DSUBU:
|
|
mips32_op = OPC_DSUBU;
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
break;
|
|
#endif
|
|
default:
|
|
gen_reserved_instruction(ctx);
|
|
goto done;
|
|
}
|
|
|
|
gen_arith(ctx, mips32_op, rz, rx, ry);
|
|
done:
|
|
;
|
|
}
|
|
break;
|
|
case M16_OPC_RR:
|
|
switch (op1) {
|
|
case RR_JR:
|
|
{
|
|
int nd = (ctx->opcode >> 7) & 0x1;
|
|
int link = (ctx->opcode >> 6) & 0x1;
|
|
int ra = (ctx->opcode >> 5) & 0x1;
|
|
|
|
if (nd) {
|
|
check_insn(ctx, ISA_MIPS_R1);
|
|
}
|
|
|
|
if (link) {
|
|
op = OPC_JALR;
|
|
} else {
|
|
op = OPC_JR;
|
|
}
|
|
|
|
gen_compute_branch(ctx, op, 2, ra ? 31 : rx, 31, 0,
|
|
(nd ? 0 : 2));
|
|
}
|
|
break;
|
|
case RR_SDBBP:
|
|
if (is_uhi(extract32(ctx->opcode, 5, 6))) {
|
|
ctx->base.is_jmp = DISAS_SEMIHOST;
|
|
} else {
|
|
/*
|
|
* XXX: not clear which exception should be raised
|
|
* when in debug mode...
|
|
*/
|
|
check_insn(ctx, ISA_MIPS_R1);
|
|
generate_exception_end(ctx, EXCP_DBp);
|
|
}
|
|
break;
|
|
case RR_SLT:
|
|
gen_slt(ctx, OPC_SLT, 24, rx, ry);
|
|
break;
|
|
case RR_SLTU:
|
|
gen_slt(ctx, OPC_SLTU, 24, rx, ry);
|
|
break;
|
|
case RR_BREAK:
|
|
generate_exception_break(ctx, extract32(ctx->opcode, 5, 6));
|
|
break;
|
|
case RR_SLLV:
|
|
gen_shift(ctx, OPC_SLLV, ry, rx, ry);
|
|
break;
|
|
case RR_SRLV:
|
|
gen_shift(ctx, OPC_SRLV, ry, rx, ry);
|
|
break;
|
|
case RR_SRAV:
|
|
gen_shift(ctx, OPC_SRAV, ry, rx, ry);
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case RR_DSRL:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_shift_imm(ctx, OPC_DSRL, ry, ry, sa);
|
|
break;
|
|
#endif
|
|
case RR_CMP:
|
|
gen_logic(ctx, OPC_XOR, 24, rx, ry);
|
|
break;
|
|
case RR_NEG:
|
|
gen_arith(ctx, OPC_SUBU, rx, 0, ry);
|
|
break;
|
|
case RR_AND:
|
|
gen_logic(ctx, OPC_AND, rx, rx, ry);
|
|
break;
|
|
case RR_OR:
|
|
gen_logic(ctx, OPC_OR, rx, rx, ry);
|
|
break;
|
|
case RR_XOR:
|
|
gen_logic(ctx, OPC_XOR, rx, rx, ry);
|
|
break;
|
|
case RR_NOT:
|
|
gen_logic(ctx, OPC_NOR, rx, ry, 0);
|
|
break;
|
|
case RR_MFHI:
|
|
gen_HILO(ctx, OPC_MFHI, 0, rx);
|
|
break;
|
|
case RR_CNVT:
|
|
check_insn(ctx, ISA_MIPS_R1);
|
|
switch (cnvt_op) {
|
|
case RR_RY_CNVT_ZEB:
|
|
tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]);
|
|
break;
|
|
case RR_RY_CNVT_ZEH:
|
|
tcg_gen_ext16u_tl(cpu_gpr[rx], cpu_gpr[rx]);
|
|
break;
|
|
case RR_RY_CNVT_SEB:
|
|
tcg_gen_ext8s_tl(cpu_gpr[rx], cpu_gpr[rx]);
|
|
break;
|
|
case RR_RY_CNVT_SEH:
|
|
tcg_gen_ext16s_tl(cpu_gpr[rx], cpu_gpr[rx]);
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case RR_RY_CNVT_ZEW:
|
|
check_insn(ctx, ISA_MIPS_R1);
|
|
check_mips_64(ctx);
|
|
tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
|
|
break;
|
|
case RR_RY_CNVT_SEW:
|
|
check_insn(ctx, ISA_MIPS_R1);
|
|
check_mips_64(ctx);
|
|
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
|
|
break;
|
|
#endif
|
|
default:
|
|
gen_reserved_instruction(ctx);
|
|
break;
|
|
}
|
|
break;
|
|
case RR_MFLO:
|
|
gen_HILO(ctx, OPC_MFLO, 0, rx);
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case RR_DSRA:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_shift_imm(ctx, OPC_DSRA, ry, ry, sa);
|
|
break;
|
|
case RR_DSLLV:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_shift(ctx, OPC_DSLLV, ry, rx, ry);
|
|
break;
|
|
case RR_DSRLV:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_shift(ctx, OPC_DSRLV, ry, rx, ry);
|
|
break;
|
|
case RR_DSRAV:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_shift(ctx, OPC_DSRAV, ry, rx, ry);
|
|
break;
|
|
#endif
|
|
case RR_MULT:
|
|
gen_muldiv(ctx, OPC_MULT, 0, rx, ry);
|
|
break;
|
|
case RR_MULTU:
|
|
gen_muldiv(ctx, OPC_MULTU, 0, rx, ry);
|
|
break;
|
|
case RR_DIV:
|
|
gen_muldiv(ctx, OPC_DIV, 0, rx, ry);
|
|
break;
|
|
case RR_DIVU:
|
|
gen_muldiv(ctx, OPC_DIVU, 0, rx, ry);
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case RR_DMULT:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_muldiv(ctx, OPC_DMULT, 0, rx, ry);
|
|
break;
|
|
case RR_DMULTU:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_muldiv(ctx, OPC_DMULTU, 0, rx, ry);
|
|
break;
|
|
case RR_DDIV:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_muldiv(ctx, OPC_DDIV, 0, rx, ry);
|
|
break;
|
|
case RR_DDIVU:
|
|
check_insn(ctx, ISA_MIPS3);
|
|
check_mips_64(ctx);
|
|
gen_muldiv(ctx, OPC_DDIVU, 0, rx, ry);
|
|
break;
|
|
#endif
|
|
default:
|
|
gen_reserved_instruction(ctx);
|
|
break;
|
|
}
|
|
break;
|
|
case M16_OPC_EXTEND:
|
|
decode_extended_mips16_opc(env, ctx);
|
|
n_bytes = 4;
|
|
break;
|
|
#if defined(TARGET_MIPS64)
|
|
case M16_OPC_I64:
|
|
funct = (ctx->opcode >> 8) & 0x7;
|
|
decode_i64_mips16(ctx, ry, funct, offset, 0);
|
|
break;
|
|
#endif
|
|
default:
|
|
gen_reserved_instruction(ctx);
|
|
break;
|
|
}
|
|
|
|
return n_bytes;
|
|
}
|